Reduction of damages to source/drain features

Patent metadata

Field	Value
Publication number	US-12477818-B2
Application number	US-202217745996-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	Oct 29, 2021
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Semiconductor structure and methods of forming the same are provided. A semiconductor structure according to the present disclosure include a substrate that includes a first region and a second region adjacent the first region, a first fin disposed over the first region, a second fin disposed over the second region, a first source/drain feature disposed over the first fin and a second source/drain feature disposed over the second fin, and an isolation structure disposed between the first fin and the second fin. The isolation structure has a protruding feature rising above the rest of the isolation structure and the protruding feature is disposed between the first fin and the second fin.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a substrate comprising a first region and a second region adjacent the first region; a first fin disposed over the first region; a second fin disposed over the second region; a first source/drain feature disposed over the first fin and a second source/drain feature disposed over the second fin; and an isolation structure disposed between the first fin and the second fin, wherein the isolation structure has a protruding feature rising above the rest of the isolation structure and the protruding feature is substantially equidistant from the first fin and the second fin, wherein a gate spacer is disposed on a top surface of the protruding feature, wherein a composition of the isolation structure is different from a composition of the gate spacer, wherein a width of the protruding feature is between about 10% and about 30% of a spacing between the first fin and the second fin.

2 . The semiconductor structure of claim 1 ,
wherein the first source/drain feature comprises silicon and an n-type dopant, wherein the second source/drain feature comprises silicon germanium and a p-type dopant.

3 . The semiconductor structure of claim 1 , further comprising:
a dielectric layer disposed over the first source/drain feature, the second source/drain feature, the isolation structure, and the protruding feature, wherein the gate spacer is disposed between the top surface of the protruding feature and the dielectric layer.

4 . The semiconductor structure of claim 3 , further comprising: a contact etch stop layer disposed between the dielectric layer and the first source/drain feature, the dielectric layer and the second source/drain feature, the dielectric layer and the isolation structure, and the dielectric layer and sidewalls of the protruding feature.

5 . The semiconductor structure of claim 4 ,
wherein the dielectric layer comprises silicon oxide, wherein the contact etch stop layer comprises silicon nitride, and wherein the gate spacer layer comprises silicon oxycarbonitride.

6 . The semiconductor structure of claim 1 , wherein a spacing between the first fin and the second fin is between about 20 nm and about 100 nm.

7 . The semiconductor structure of claim 6 ,
wherein the protruding feature comprises a height between about 10 nm and about 25 nm.

8 . The semiconductor structure of claim 1 , wherein a dielectric constant of the gate spacer is smaller than a dielectric constant of silicon nitride.

9 . A semiconductor structure, comprising:
a substrate comprising a first region and a second region adjacent the first region; a first fin and a second fin disposed over the first region; a third fin and a fourth fin disposed over the second region; an isolation structure disposed between the first fin and the second fin, between the first fin and the third fin, and between the third fin and the fourth fin; a first source/drain feature extending continuously from over the first fin to over the second fin; and a second source/drain feature extending continuously from over the third fin to over the fourth fin, wherein the isolation structure comprises a protruding feature rising above the rest of the isolation structure and the protruding feature is substantially equidistant from the first fin and the third fin, wherein the first fin is closer to the third fin and the second fin is farther away from the third fin, wherein the third fin is closer to the first fin and the fourth fin is farther away from the first fin.

10 . The semiconductor structure of claim 9 , further comprising:
a dielectric layer disposed over the isolation structure, the first source/drain feature, the second source/drain feature, and the protruding feature, wherein the protruding feature extends into the dielectric layer.

11 . The semiconductor structure of claim 10 , further comprising:
a gate spacer layer sandwiched between a top surface of the protruding feature and the dielectric layer.

12 . The semiconductor structure of claim 11 , wherein a composition of the gate spacer layer is different from a composition of the protruding feature.

13 . The semiconductor structure of claim 11 , further comprising:
a contact etch stop layer disposed between the dielectric layer and the first source/drain feature, the dielectric layer and the second source/drain feature, the dielectric layer and the isolation structure, and the dielectric layer and sidewalls of the protruding feature.

14 . The semiconductor structure of claim 13 ,
wherein the dielectric layer comprises silicon oxide, wherein the contact etch stop layer comprises silicon nitride, and wherein the gate spacer layer comprise silicon oxycarbonitride.

15 . The semiconductor structure of claim 10 ,
wherein the first source/drain feature comprises silicon and an n-type dopant, wherein the second source/drain feature comprises silicon germanium and a p-type dopant.

16 . A method, comprising:
receiving a workpiece comprising:
a substrate comprising a first region and a second region, and
a first fin over the first region and comprising a first source/drain region,
a second fin over the second region and comprising a second source/drain region,
an isolation feature over the substrate such that a top portion of the first fin and a top portion of the second fin rise above the isolation feature;
depositing a gate spacer layer over the isolation feature, the first source/drain region, and the second source/drain region; after the depositing of the gate spacer layer, forming a first pattern mask over the second fin, wherein an edge of the first pattern mask is closer to the first fin than the second fin; etching the first region and the first source/drain region using the first pattern mask as an etch mask; forming a first source/drain feature over the first source/drain region; forming a second pattern mask over the first source/drain feature and the first fin, wherein an edge of the second pattern mask is closer to the second fin than the first fin; and etching the second region using the second pattern mask as an etch mask, wherein the etching of the second region forms a protruding feature from the isolation feature and the protruding feature is disposed between the first fin and the second fin, wherein a top surface of the protruding feature is covered by the gate spacer layer.

17 . The method of claim 16 , wherein a portion of the gate spacer layer is disposed on the protruding feature after the etching of the second region.

18 . The method of claim 16 , further comprising:
forming a dummy gate stack over a first channel region of the first fin and a second channel region of the second fin, wherein the forming of the gate spacer layer comprises depositing the gate spacer layer over the dummy gate stack.

19 . The method of claim 16 , wherein the etching of the first region reduces a thickness of the isolation feature in the first region by between about 10 nm and about 25 nm.

20 . The method of claim 16 , wherein the etching of the second region reduces a thickness of the isolation feature in the second region by between about 10 nm and about 25 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Hsin Yang
• Dai Wei-Syuan
• Chiang Tsung-Yu
• Chen Lung

Classifications

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0188 Primary

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017 Primary

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title