Semiconductor device

Patent metadata

Field	Value
Publication number	US-12477788-B2
Application number	US-202318106106-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	May 17, 2017
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

First claim

The invention claimed is:

1 . A semiconductor device comprising:
a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side; a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer; a trench source structure including a source trench formed deeper than the gate trench and formed across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench; a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench; a source region of the first conductivity type formed in a surface layer portion of the body region; a drain electrode connected to the second main surface of the semiconductor layer; and an outer well region of the second conductivity region formed in an outer region outside of a region where the trench gate structure is formed, wherein an aspect ratio of the trench source structure is greater than an aspect ratio of the trench gate structure.

2 . The semiconductor device according to claim 1 , wherein the aspect ratio of the trench source structure is not less than 0.5 and not more than 18.0.

3 . The semiconductor device according to claim 1 , wherein a depletion layer spreads further from a boundary region between the semiconductor layer and the well region toward a region of a second main surface side than from a bottom wall of the gate trench in the semiconductor layer toward a region of the second main surface side.

4 . The semiconductor device according to claim 3 , wherein the depletion layer overlaps to the bottom wall of the gate trench.

5 . The semiconductor device according to claim 1 , wherein the well region is formed in a region of the semiconductor layer along a side wall of the source trench.

6 . The semiconductor device according to claim 1 , wherein the well region is formed in a region of the semiconductor layer along a bottom wall of the source trench.

7 . The semiconductor device according to claim 1 , wherein the well region is formed continuously in a region of the semiconductor layer along a side wall, a bottom wall, and a corner portion connecting the side wall and the bottom wall of the source trench.

8 . The semiconductor device according to claim 1 , wherein the well region is connected to the body region.

9 . The semiconductor device according to claim 1 , wherein the trench source structure includes a barrier forming layer interposed in a region between the source trench and the source electrode and having a higher potential barrier than a potential barrier between the well region and the source electrode.

10 . The semiconductor device according to claim 9 , wherein the barrier forming layer includes an insulating barrier forming layer made of an insulating material.

11 . The semiconductor device according to claim 9 , wherein the barrier forming layer includes a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

12 . The semiconductor device according to claim 9 , wherein the barrier forming layer includes an insulating barrier forming layer made of an insulating material, and a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

13 . The semiconductor device according to claim 9 , wherein the barrier forming layer is formed along a side wall, a bottom wall, and a corner portion connecting the side wall and the bottom wall of the source trench.

14 . The semiconductor device according to claim 1 , further comprising: a contact region of the second conductivity type formed in a region of the semiconductor layer along a side wall of the source trench and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the body region.

15 . The semiconductor device according to claim 1 , further comprising: a contact region of the second conductivity type formed in a region of the semiconductor layer along a bottom wall of the source trench and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the body region.

16 . The semiconductor device according to claim 1 , wherein part of the first main surface is recessed and forming a recessed region, the outer well region is formed in the recessed region.

17 . A semiconductor device comprising:
a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side; a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer; a trench source structure including a source trench formed deeper than the gate trench and formed across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench; a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench; a source region of the first conductivity type formed in a surface layer portion of the body region; a drain electrode connected to the second main surface of the semiconductor layer; and an outer well region of the second conductivity region formed in an outer region outside of a region where the trench gate structure is formed, wherein the trench source structure includes a barrier forming layer interposed in a region between the source trench and the source electrode and having a higher potential barrier than a potential barrier between the well region and the source electrode, and wherein the barrier forming layer includes an insulating barrier forming layer made of an insulating material, and a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

Assignees

• Rohm Co Ltd
• Rohm Ltd

Inventors

• Nakagawa Minoru
• Nakano Yuki
• Aketa Masatoshi
• Ueno Masaya
• Mori Seigo
• Yamamoto Kenji

Classifications

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title