Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same

Patent metadata

Field	Value
Publication number	US-12477770-B2
Application number	US-202318523174-A
Country	US
Kind code	B2
Filing date	Nov 29, 2023
Priority date	Jun 24, 2016
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

First claim

What is claimed is:

1 . An apparatus, comprising:
a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate; wherein the source is electrically connected to the p-region; wherein the p-region is below the group III-Nitride barrier layer and the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer; wherein the p-region extends to a point before a proximal edge of the gate and the p-region is at most under only part of the gate; and wherein the proximal edge of the gate is located on the group III-Nitride barrier layer and on a source side of the gate.

2 . The apparatus of claim 1 , further comprising a first connection, wherein the source is electrically connected to the p-region through the first connection.

3 . The apparatus of claim 2 , wherein the first connection extends between a p-type material contact and the source.

4 . The apparatus of claim 2 , wherein the first connection comprises at least one conductive metallic material.

5 . The apparatus of claim 2 , wherein the first connection comprises a metallization.

6 . The apparatus of claim 2 , further comprising a spacer layer, wherein the first connection comprises in part a metallization on the spacer layer.

7 . The apparatus of claim 1 , further comprising a p-type material contact, wherein the p-type material contact is arranged on the p-region.

8 . The apparatus of claim 7 , wherein the p-type material contact is electrically coupled to the p-region and the p-type material contact comprises one or more metal overlayers.

9 . The apparatus of claim 7 , wherein the p-type material contact is formed in or on the group III-Nitride barrier layer.

10 . The apparatus of claim 7 , wherein the p-type material contact is formed in or on the group III-Nitride buffer layer.

11 . The apparatus of claim 7 , further comprising a region or area under or adjacent the p-type material contact comprising implanted p-dopants and/or doped with p-dopants to form an electrical connection with the p-region.

12 . The apparatus of claim 7 , further comprising a recess,
wherein the p-type material contact is arranged in the recess.

13 . The apparatus of claim 7 , wherein the p-type material contact comprises at least one metal overlayer.

14 . The apparatus of claim 12 , wherein the recess is provided in the group III-Nitride buffer layer and the group III-Nitride barrier layer.

15 . The apparatus of claim 12 , wherein the recess extends down to the p-region.

16 . The apparatus of claim 12 , wherein the recess extends down to the group III-Nitride buffer layer.

17 . The apparatus of claim 12 , wherein the p-type material contact is formed in or on the group III-Nitride buffer layer in the recess provided down to the group III-Nitride buffer layer.

18 . The apparatus of claim 12 , wherein the recess is created by removing at least part of the group III-Nitride barrier layer and at least part of the group III-Nitride buffer layer.

19 . The apparatus of claim 2 , further comprising a field plate.

20 . The apparatus of claim 19 , further comprising a second connection connected to the field plate and the source.

21 . The apparatus of claim 20 , wherein the field plate is electrically connected to the source through the second connection.

22 . The apparatus of claim 19 , wherein the first connection and a second connection are configured to connect the field plate to a p-type material contact.

23 . The apparatus of claim 20 , wherein the first connection and the second connection are configured to connect the field plate to a p-type material contact.

24 . The apparatus of claim 1 , wherein the p-region comprises implanted materials.

25 . The apparatus of claim 1 , wherein the p-region is in the substrate below said group III-Nitride barrier layer.

26 . The apparatus of claim 1 , further comprising an epitaxial layer on the substrate and the p-region is in the epitaxial layer.

27 . The apparatus of claim 1 , wherein the p-region is arranged solely in the substrate below said group III-Nitride barrier layer.

28 . The apparatus of claim 1 , further comprising an epitaxial layer on the substrate and the p-region is arranged solely in the epitaxial layer.

29 . The apparatus of claim 1 , further comprising a field plate, wherein the field plate is electrically coupled to said source.

30 . An apparatus, comprising:
a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer: a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate; a field plate, wherein the source is electrically connected to the p-region; wherein the p-region is below the group III-Nitride barrier layer and the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer; wherein the p-region extends to a point before a proximal edge of the gate; wherein the proximal edge of the gate is located on the group III-Nitride barrier layer and on a source side of the gate; wherein the field plate is electrically coupled to said source; and wherein the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer such that the p-region is not located vertically under the gate.

31 . The apparatus of claim 29 , wherein the p-region is structured and arranged to extend an entire length parallel to the group III-Nitride barrier layer.

32 . The apparatus of claim 1 , wherein the p-region extends to a point within about 0 to about 0.3 um of the proximal edge.

33 . The apparatus of claim 1 , wherein the p-region extends to the proximal edge.

34 . The apparatus of claim 1 , wherein the p-region extends 0% to 20% of a gate length past the proximal edge.

35 . The apparatus of claim 1 , wherein the p-region extends 20% to 40% of a gate length past the proximal edge.

36 . The apparatus of claim 1 , wherein the p-region extends 40% to 60% of a gate length past the proximal edge.

37 . The apparatus of claim 1 , wherein the p-region extends 60% to 80% of a gate length past the proximal edge.

38 . A method of making a device comprising:
providing a substrate; providing a group III-Nitride buffer layer on the substra

Assignees

• Wolfspeed Inc

Inventors

• Sriram Saptharishi
• Smith Thomas J
• Suvorov Alexander
• Hallin Christer

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D64/411

  for FETs · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title

• H10D64/111

  Field plates · CPC title