Low power and area clock monitoring circuit using ring delay arrangement for clock signal having phase-to-phase variation

Patent metadata

Field	Value
Publication number	US-12476785-B2
Application number	US-202318295537-A
Country	US
Kind code	B2
Filing date	Apr 4, 2023
Priority date	Apr 4, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. The method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.

First claim

What is claimed is:

1 . A clock monitoring circuit for monitoring a clock signal having phase-to-phase variation, comprising:
a binary adder configured to add a fixed number of tune bits to a pulse count of a reference phase instance for a selected one of a high phase count or low phase count of the clock signal to yield a modified added pulse count for the reference phase instance when detecting a clock slow clock abnormality; a binary subtractor configured to subtract the fixed number of tune bits from the pulse count of the reference phase instance for the selected one of the high phase count or low phase count of the clock signal to yield a modified subtracted pulse count for the reference phase instance when detecting a clock fast clock abnormality; a first comparator configured to compare the modified added pulse count to a pulse count for an immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal when detecting the clock slow clock abnormality; a second comparator configured to compare the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal when detecting the clock fast clock abnormality; two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of the clock signal; and two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators, wherein a count of the number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal.

2 . The clock monitoring circuit as recited in claim 1 , further comprising:
clock slow detection (CSD) circuitry configured to assert a CSD signal when the modified added pulse count for the reference phase is less than the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal; clock fast detection (CFD) circuitry configured to assert a CFD_synch signal with the modified subtracted pulse count for the reference phase is greater than the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal; and a logic function configured to assert a clock abnormality detect (CAD) signal when either the CSD or CFD_synch signal are asserted.

3 . The clock monitoring circuit as recited in claim 1 , wherein the two ring pulse generators each comprise a plurality of edge detector circuits implemented in a ring delay arrangement wherein an output of a last of the plurality of edge detector circuits is fed back to an input of a first of the plurality of edge detector circuits.

4 . The clock monitoring circuit as recited in claim 3 , wherein:
a first edge detector circuit of the plurality of edge detector circuits of a first ring pulse generator detects a first edge of the clock signal monitored by the clock monitoring circuit and outputs a pulse with a unit pulse width to a subsequent edge detector circuit of the plurality of edge detector circuits; and when the subsequent edge detector circuit detects an edge of the pulse output by the first edge detector, the subsequent edge detector outputs a pulse with the unit pulse width to another subsequent edge detector circuit of the plurality of edge detector circuits of the first ring pulse generator.

5 . The clock monitoring circuit as recited in claim 4 , wherein:
the first edge of the clock signal monitored by the clock monitoring circuit is a falling edge; and an edge of the pulse output by the first edge detector detected by subsequent edge detector circuits are a falling edge.

6 . The clock monitoring circuit as recited in claim 3 , wherein the unit pulse width output by the plurality of edge detectors for both the first and second ring pulse generators is a same pulse width.

7 . The clock monitoring circuit as recited in claim 1 , wherein:
separate n-bit counters are reset at a beginning of each of their respective separate phases of the clock signal; and the resetting is delayed until after a last pulse is counted for each of the respective phases of the clock signal.

8 . An integrated circuit (IC), comprising:
at least one processing subsystem; and at least one clock monitoring circuit for monitoring a clock signal having phase-to-phase variation coupled to the at least one processing subsystem and a clock signal externally generated from the IC or a plurality of clock signals generated internal to the IC, wherein the at least one clock monitoring circuit comprises:
a binary adder configured to add a fixed number of tune bits to a pulse count of a reference phase instance for a selected one of a high phase count or low phase count of the clock signal to yield a modified added pulse count for the reference phase instance when detecting a clock slow clock abnormality;
a binary subtractor configured to subtract the fixed number of tune bits from the pulse count of the reference phase instance for the selected one of the high phase count or low phase count of the clock signal to yield a modified subtracted pulse count for the reference phase instance when detecting a clock fast clock abnormality;
a first comparator configured to compare the modified added pulse count to a pulse count for an immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal when detecting the clock slow clock abnormality;
a second comparator configured to compare the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal when detecting the clock fast clock abnormality;
two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of the clock signal; and
two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators wherein a count of number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal.

9 . The IC as recited in claim 8 , further comprising:
clock slow detection (CSD) circuitry configured to assert a CSD signal when the modified added pulse count for the reference phase is less than the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal; clock fast detection (CFD) circuitry configured to assert a CFD_synch signal with the modified subtracted pulse count for the reference phase is greater than the pulse count for the immediately subsequent phase instance of the selected one of the high phase count or low phase count of the clock signal; and a logic function configured to assert a clock abnormality detect (CAD) signal when either the CSD or CFD_synch signal are asserted.

10 . The IC as recited in claim 8 , further comprising phase-locked loop circuits (PLLs) that generate the plurality of clock signals generated internal to the IC.

11 . The IC as recited in claim 8 , wherein the at least one processing subsystem includes one or more central processing units (CPUs), one or more graphics processing units (GPUs), or one or more memory controllers.

12 . The IC as recit

Assignees

• Nvidia Corp

Inventors

• Rajpathak Kedar
• Raja Tezaswi

Classifications

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H03K5/1534

  Transition or edge detectors · CPC title

• H03K5/06

  by the use of delay lines or other analogue delay elements · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title