Reception circuit

Patent metadata

Field	Value
Publication number	US-12476596-B2
Application number	US-202017791430-A
Country	US
Kind code	B2
Filing date	Dec 10, 2020
Priority date	Jan 16, 2020
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Provided is a reception circuit that suppresses skew of a waveform of a signal and enables high-speed data communication.
A reception circuit according to the present disclosure includes: a first differential stage that receives a first input signal and a second input signal at a first input unit and a second input unit, respectively, and causes first and second currents corresponding to the first and second input signals, respectively, to flow; a second differential stage including a first current path that generates and outputs a first amplified signal corresponding to the first current and a second current path that generates and outputs a second amplified signal corresponding to the second current; a power supply line that supplies power to the first and second differential stages; and at least one variable resistance unit provided in the first or second current path.

First claim

The invention claimed is:

1 . A reception circuit, comprising:
a first differential stage configured to:
receive a first input signal at a first input unit and a second input signal at a second input unit; and
cause a first current to flow corresponding to the first input signal and a second current to flow corresponding to the second input signal;
a second differential stage including a first current path configured to output a first amplified signal corresponding to the first current and a second current path configured to output a second amplified signal corresponding to the second current; a power supply line configured to supply power to the first differential stage and the second differential stage; at least one variable resistance unit in the first current path or the second current path; a DC power supply configured to input a DC signal having substantially a same voltage to each of the first input unit and the second input unit; one or a plurality of buffer circuits that is connected to an output of the second differential stage, and is configured to:
amplify the first amplified signal to output a third amplified signal; and
amplify the second amplified signal to output a fourth amplified signals; and
a comparison circuit configured to compare the third amplified signal and the fourth amplified signal based on the input of the DC signal to each of the first input unit and the second input unit,
wherein the at least one variable resistance unit is set so that a voltage difference between the third amplified signal and the fourth amplified signal decreases.

2 . The reception circuit according to claim 1 , wherein the at least one variable resistance unit includes:
a first variable resistor in the first current path, and a second variable resistor in the second current path.

3 . The reception circuit according to claim 1 , further comprising a storage unit that is configured to store a resistance value of the at least one variable resistance unit.

4 . The reception circuit according to claim 1 , wherein the at least one variable resistance unit includes:
a first resistance block including a plurality of first resistance elements connected in parallel and a first switch between the plurality of first resistance elements, and a second resistance block including a plurality of second resistance elements connected in parallel and a second switch between the plurality of second resistance elements, and the first resistance block and the second resistance block are connected in series between the power supply line and one of the first current path or the second current path.

5 . The reception circuit according to claim 1 , wherein the comparison circuit is further configured to compare the first amplified signal and the second amplified signal when the DC signal is input to the first input unit and the second input unit,
wherein the at least one variable resistance unit is set so that a voltage difference between the first amplified signal and the second amplified signal decreases.

6 . The reception circuit according to claim 1 , further comprising:
a first switch between the DC power supply and the first input unit; and a second switch between the DC power supply and the second input unit.

7 . The reception circuit according to claim 6 , wherein the first switch and the second switch are brought into a conductive state in a case where the DC signal is input from the DC power supply to the first input unit and the second input unit, and
the first switch and the second switch are brought into a non-conductive state in a case where the first input signal is input to the first input unit and the second input signal is input to the second input unit as mutually complementary high frequency signals.

8 . The reception circuit according to claim 1 , further comprising:
a first amplification unit and a second amplification unit, wherein each of the first amplification unit and the second amplification unit includes the first differential stage, the second differential stage, the power supply line, and the at least one variable resistance unit, wherein the first amplification unit is configured to receive mutually complementary data signals from a transmission circuit, and the second amplification unit is configured to receive mutually complementary clock signals from the transmission circuit.

9 . The reception circuit according to claim 1 , wherein the at least one variable resistance unit is between the power supply line and a transistor in the first current path or the second current path.

10 . The reception circuit according to claim 1 , wherein the at least one variable resistance unit is between a transistor in the first current path or the second current path and a ground terminal.

11 . The reception circuit according to claim 5 , further comprising:
a resistance control circuit that is configured to:
change a resistance value of the at least one variable resistance unit stepwise so that a voltage difference between the first amplified signal and the second amplified signal decreases on a basis of a comparison result of the comparison circuit; and
set the resistance value of the at least one variable resistance unit on a basis of inversion of polarity of the voltage difference between the first amplified signal and the second amplified signal; and
a storage unit that is configured to store the resistance value of the at least one variable resistance unit.

12 . The reception circuit according to claim 3 , wherein the storage unit is further configured to store a set resistance value of the at least one variable resistance unit as a non-rewritable value.

13 . The reception circuit according to claim 3 , wherein the storage unit is further configured to store a setting of a set resistance value of the at least one variable resistance unit to be rewritable.

14 . The reception circuit according to claim 11 , wherein the resistance control circuit is further configured to set the resistance value of the at least one variable resistance unit in a period between:
a time when the first input unit receives the first input signal and the second input unit receives the second input signal,
wherein the first input signal and the second input signal are complementary to each other in scanning of a first scanning line of an image; and
a time when scanning of a second scanning line next to the first scanning line starts.

15 . A reception circuit, comprising:
a first amplification unit and a second amplification unit, wherein each of the first amplification unit and the second amplification unit comprises: a first differential stage configured to:
receive a first input signal at a first input unit and a second input signal at a second input unit; and
cause a first current to flow corresponding to the first input signal and a second current to flow corresponding to the second input signal;
a second differential stage including a first current path configured to output a first amplified signal corresponding to the first current and a second current path configured to output a second amplified signal corresponding to the second current; a power supply line configured to supply power to the first differential stage and the second differential stage; and at least one variable resistance unit in the first current path or the second current path;
wherein the first amplification unit is configured to receive mutually complementary data signals from a transmission circuit, and
the second amplification unit is configured to receive mutually complementary

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Nakao Hiroshi
• Yanase Naoto

Classifications

• H03F1/22

  by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively · CPC title

• H04L25/0292

  Arrangements specific to the receiver end · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45652

  the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade · CPC title