Cascaded resonant switched-capacitor power converter

US12476534B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12476534-B2
Application numberUS-202318201641-A
CountryUS
Kind codeB2
Filing dateMay 24, 2023
Priority dateJun 7, 2022
Publication dateNov 18, 2025
Grant dateNov 18, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A cascaded power converter architecture is provided which merges a front end stage with subsequent interleaved Switched Capacitor (SC) stages to achieve high conversion ratios. This interleaving control technique addresses practical conversion challenges. Numerous topologies can be created from this approach, a number of examples being depicted, including: (a) a two stage 4-to-1 conversion using two 2-to-1 ReSc converter stages, and (b) 8-to-1 converters with (b)(i) a 2-to-1 ReSC stage followed by a 2nd stage having four 4-to-1 STC converter phases, (b)(ii) a 2-to-1 ReSC 1st stage followed by a 2nd stage with four 4-to-1 series-parallel phases, and (c) a multi-stage cascading three stage converter with a 2-to-1 ReSC 1st stage, a 2nd stage of two 2-to-1 ReSC phases, and a 3rd stage having four 2-to-1 ReSC phases.

First claim

Opening claim text (preview).

What is claimed is: 1 . A cascaded resonant switched-capacitor converter apparatus, comprising: (a) a single first stage circuit having an input directed through a first set of switches to a capacitance, which is connected through a second set of switches through an inductor as an output of the first stage; (b) at least one second stage circuit comprising two or more resonant switched capacitor converters, each having switches on either side of a charge storage element, and whose outputs are merged as an output of the apparatus; (c) an intermediate capacitor, C mid , between the first stage circuit and said at least one second stage circuit; and (d) wherein said first stage circuit and said at least one second stage circuit are multiple stages of resonant converters coupled in an interleaving manner so that the input current of the second stage matches the output current of the first stage, which means that the value of capacitance of C mid does not provide complete decoupling of the first stage and second stage thereby reducing C mid capacitance value requirements and reducing capacitance volume, while maintaining circuit performance; and (e) wherein drive signals are generated to control the state of the switches in the first stage and second stage of conversion, and wherein these signals are constrained by a time delays to create an overlapping non-active state to assure that both first switches are not simultaneously active, and that both second switches are not simultaneously active. 2 . A cascaded resonant switched-capacitor converter apparatus, comprising: (a) a single first stage circuit having an input directed to a resonant capacitance through switches, a first set of switches on a first side of the resonant capacitor and a second set of switches on a second side of the resonant capacitor, and which is connected through switching to an inductance at a first stage output, wherein said capacitance and inductance operate as a first LC tank circuit of the resonant switched-capacitor matrix; (b) wherein said first stage comprises a single phase circuit, having a first half cycle of the period in which switches are activated for charging said first LC tank circuit, while in a second half cycle of the period, said first LC tank circuit is discharged into a subsequent stage; (c) circuitry of at least one subsequent stage comprising at least two converters, which receives input from a preceding stage, each one of said at least one subsequent stage containing multiple circuit phases which are interleaved; (d) wherein each circuit phase of each of said at least one subsequent stage is configured with switches configured for switching power to and from one or more capacitances, or capacitances and inductances, for charging tank circuitry of this circuit phase from its input and discharging tank circuitry of this circuit phase into an output which drives a load, or a subsequent circuit stage, wherein said first LC tank circuit is alternately coupled between a tank circuit in a first of the multiple circuit phases, and a tank circuit in a second of the multiple circuit phase which provides interleaving of these circuit phases; and (e) wherein said multiple circuit phases improve current-handling capability of their associated stage, since each circuit phase handles a portion of the total current load, and wherein each of said multiple circuit phases has a resonant frequency which matches that of said first stage; (f) wherein each circuit phase of each of said at least one subsequent stage is configured for receiving power from a specific output waveform phase from the preceding circuit stage and interleaving outputs with that of the other circuit phases into the output from this same stage; and (g) wherein drive signals are generated to control the state of the switches in the first stage and second stage of conversion, and wherein these signals are constrained by time delays to create an overlapping non-active state to assure that both first switches are not simultaneously active, and that both second switches are not simultaneously active. 3 . The apparatus of claim 2 , wherein the apparatus provides a 4-to-1 conversion ratio between a voltage input and an output voltage, or can be operated in the reverse direction for voltage step-up. 4 . The apparatus of claim 2 , wherein the second stage circuit comprises two phases of interleaved circuitry. 5 . The apparatus of claim 2 , wherein the first stage circuit comprises a single-phase 2-to-1 resonant switched-capacitor (ReSC) circuit and wherein the second stage circuit comprises two phases of interleaved 2-to-1 ReSC circuitry to realize a total 4-to-1 conversion ratio. 6 . The apparatus of claim 2 , wherein the apparatus has a first resonant state and a second resonant state. 7 . The apparatus of claim 2 , wherein the first stage circuit and the second stage circuit are resonant at a same resonant frequency. 8 . The apparatus of claim 2 , wherein said apparatus has a switching frequency that is equal to or greater than the resonant frequency. 9 . The apparatus of claim 2 , wherein each switch can realize zero current switching by using a ZCS control signal scheme. 10 . The apparatus of claim 2 , wherein the intermediate capacitor C mid does not participate in circuit resonance. 11 . The apparatus of claim 2 , wherein said at least one subsequent stage comprises two phases of 4-to-1 switched tank converter (STC), wherein the overall conversion ratio is 8 to 1. 12 . The apparatus of claim 2 , wherein said at least one subsequent stage comprises a second stage having four phases of 4-to-1 series-parallel phases, wherein the overall conversion ratio is 8 to 1, or can be operated in the reverse direction for voltage step-up. 13 . The apparatus of claim 2 , wherein said at least one subsequent stage comprises a second and third stage of multiple phases. 14 . The apparatus of claim 13 , wherein said second stage comprises two phases. 15 . The apparatus of claim 14 , wherein said third stage comprises four phases. 16 . A cascaded resonant switched-capacitor converter apparatus, comprising: (a) a first stage comprising a single-phase 2-to-1 resonant switched-capacitor (ReSC) circuit having an input directed through a first set of switches to a capacitance, which is connected through a second set of switches through an inductor as an output of the first stage; (b) a second stage comprising two phases of interleaved 2-to-1 ReSC circuitry to realize a total 4-to-1 conversion ratio comprising two or more resonant switched capacitor converters, each having switches on either side of a charge storage element, and whose outputs are merged as an output of the apparatus; (c) wherein outputs from the switching paths of said first stage are coupled through an inductance for coupling to an intermediate capacitance C mid in said second stage; (d) wherein said second stage has said two phases operating in an interleaved manner in which input current to said second stage matches output current from said first stage, thereby eliminating requirements for a larger intermediate capacitance C mid to completely decouple the first stage and second stage thereby reducing C mid capacitance value requirements and associated capacitance volume, while maintaining circuit performance; and (e) wherein drive signals are generated to control the state of the switches in the first stage and second stage of conversion, and wherein these signals are constrained by time delays to create an overlapping non-active state to assure that both first switches a

Assignees

Inventors

Classifications

  • H02M3/01Primary

    Resonant DC/DC converters · CPC title

  • using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • with parallel connected charge pump stages · CPC title

  • including plural semiconductor devices as final control devices for a single load · CPC title

  • Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

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What does patent US12476534B2 cover?
A cascaded power converter architecture is provided which merges a front end stage with subsequent interleaved Switched Capacitor (SC) stages to achieve high conversion ratios. This interleaving control technique addresses practical conversion challenges. Numerous topologies can be created from this approach, a number of examples being depicted, including: (a) a two stage 4-to-1 conversion usin…
Who is the assignee on this patent?
Univ California
What technology area does this patent fall under?
Primary CPC classification H02M3/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).