Bidirectional power switch circuit

Patent metadata

Field	Value
Publication number	US-12476532-B2
Application number	US-202318524821-A
Country	US
Kind code	B2
Filing date	Nov 30, 2023
Priority date	Dec 1, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

The disclosure relates to improvements in bidirectional power switch circuits. Example embodiments include a bidirectional power switch, BPS, circuit ( 200 ) comprising: first and second terminals ( 203, 204 ); first and second MOSFETs ( 201, 202, 501, 502 ) connected in series between the first and second terminals ( 203, 204 ) and comprising respective first and second source to body diodes (Dsb, Dsb 1 , Dsb 2 ); first and second power supply rails (VDD, VEE); first, second, third, fourth and fifth switchable current sources (IDD 1 - 3 , SD 1 - 3 , IEE 1 - 2 , SE 1 - 2 ); first and second resistors (Rbs, Rgs); and a BPS switching controller ( 206 ) configured to control operation of the BPS circuit ( 200 ) between a BPS ON state in which the first and second terminals ( 203, 204 ) are connected and a BPS OFF state in which the first and second terminals ( 203, 204 ) are disconnected.

First claim

The invention claimed is:

1 . A bidirectional power switch (BPS) circuit comprising:
first and second terminals; first and second MOSFETs connected in series between the first and second terminals and comprising respective first and second source to body diodes; first and second power supply rails; a first switchable current source connected between the first power supply rail and a body terminal of the first MOSFET; a second switchable current source connected between the first power supply rail and a common node connected to a source terminal of each of the first and second MOSFETs; a third switchable current source connected between one of the first and second power supply rails and a gate terminal of the first MOSFET; a fourth switchable current source connected between the second power supply rail and the body terminal of the first MOSFET; a fifth switchable current source connected between the second power supply rail and the common node; a first resistor connected between the body terminal of the first MOSFET and the common node; a second resistor connected between the gate terminal of the first MOSFET and the common node; and a BPS switching controller configured to control operation of the BPS circuit between a BPS ON state in which the first and second terminals are connected through the first and second MOSFETs and a BPS OFF state in which the first and second terminals are disconnected.

2 . The BPS circuit of claim 1 , further comprising:
a sixth switchable current source connected between the first power supply rail and a body terminal of the second MOSFET; a seventh switchable current source connected between the second power supply rail and the body terminal of the second MOSFET; and a third resistor connected between the body terminal of the second MOSFET and the common node, wherein the gate terminals of the first and second MOSFETs are connected to each other.

3 . The BPS circuit of claim 2 , wherein the first and second MOSFETs are P-channel MOSFETs and an anode of each of the first and second source to body diodes is connected to the common node.

4 . The BPS circuit of claim 3 , wherein the third switchable current source is connected between the first power supply rail and the gate terminals of the first and second MOSFETs.

5 . The BPS circuit of claim 2 , comprising a current switching controller configured to operate the first, second, third, fourth, and fifth switchable current sources.

6 . The BPS circuit of claim 5 , wherein the current switching controller is configured, in the BPS OFF state, to switch on the first, fifth and seventh switchable current sources to apply a reverse bias voltage across the first and second source to body diodes.

7 . The BPS circuit of claim 5 , wherein the current switching controller is configured, in the BPS OFF state, to switch on the third and fifth switchable current sources to apply a positive gate to source voltage across the first and second MOSFETs.

8 . The BPS circuit of claim 5 , wherein the current switching controller is configured, in the BPS ON state, to switch on the second, fourth and seventh switchable current sources to apply a forward bias voltage across the first and second source to body diodes.

9 . The BPS circuit of claim 2 , wherein the first and second MOSFETs are N-channel MOSFETs and a cathode of each of the first and second source to body diodes is connected to the common node.

10 . The BPS circuit of claim 9 , wherein the third switchable current source is connected between the second power supply rail and the gate terminals of each of the first and second MOSFETs.

11 . The BPS circuit of claim 9 , comprising a current switching controller configured, in the BPS OFF state, to switch on the second, fourth and seventh switchable current sources to apply a reverse bias voltage across the first and second source to body diodes.

12 . The BPS circuit of claim 11 , wherein the current switching controller is configured, in the BPS OFF state, to switch on the second and third switchable current sources to apply a positive source to gate voltage across the first and second MOSFETs.

13 . The BPS circuit of claim 11 , wherein the current switching controller is configured, in the BPS ON state, to switch on the first, fifth and sixth switchable current sources to apply a forward bias voltage across the first and second source to body diodes.

14 . A method of operating a bidirectional power switch (BPS) circuit, the BPS circuit comprising:
first and second terminals; first and second MOSFETs connected in series between the first and second terminals and comprising respective first and second source to body diodes; first and second power supply rails; switchable current sources comprising:
a first switchable current source connected between the first power supply rail and a body terminal of the first MOSFET;
a second switchable current source connected between the first power supply rail and a common node connected to a source terminal of each of the first and second MOSFETS;
a third switchable current source connected between one of the first and second power supply rails and a gate terminal of the first MOSFET;
a fourth switchable current source connected between the second power supply rail and the body terminal of the first MOSFET; and
a fifth switchable current source connected between the second power supply rail and the common node;
a first resistor connected between the body terminal of the first MOSFET and the common node; a second resistor connected between the gate terminal of the first MOSFET and the common node; and a BPS switching controller configured to control operation of the BPS circuit between a BPS ON state in which the first and second terminals are connected through the first and second MOSFETs and a BPS OFF state in which the first and second terminals are disconnected, the method comprising:
in a BPS ON state, operating the switchable current sources to apply a forward bias voltage across the first and second source to body diodes; and
in a BPS OFF state, operating the switchable current sources to apply a reverse bias voltage across the first and second source to body diodes.

15 . The method of claim 14 , wherein the first and second MOSFETs are P-channel MOSFETs and, in the BPS OFF state, the switchable current sources are operated to apply a positive gate to source voltage across the first and second MOSFETs.

16 . The method of claim 15 , wherein, in the BPS OFF state, a current switching controller switches on at least the first and fifth switchable current sources to apply a reverse bias voltage across the first and second source to body diodes.

17 . The method of claim 16 , wherein, in the BPS OFF state, the current switching controller switches on the third and fifth switchable current sources to apply a positive gate to source voltage across the first and second MOSFETs.

18 . The method of claim 16 , wherein, in the BPS ON state, the current switching controller switches on at least the second and fourth switchable current sources to apply a forward bias voltage across the first and second source to body diodes.

19 . The method of claim 14 , wherein the first and second MOSFETs are N-channel MOSFETs and, in the BPS OFF state, the switchable current sources are operated to apply a positive source to gate voltage across the first and second MOSFETs.

20 . The method of claim 19 , wherein, in the BPS OFF state, a current switching controller

Assignees

• Nxp Usa Inc

Inventors

• Paladugu Ranga Seshu
• Lim Soon G
• Trivedi Ronak Prakashchandra
• Morello Carmelo

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K17/161

  in field-effect transistor switches · CPC title