Power divider supporting different numbers of outputs

Patent metadata

Field	Value
Publication number	US-12476342-B2
Application number	US-202318536217-A
Country	US
Kind code	B2
Filing date	Dec 11, 2023
Priority date	Dec 11, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A device configured to support different numbers of outputs. The device includes an input port configured to receive an input signal. The device also includes a first transmission line characterized by a first characteristic impedance and coupled to a first output port. A switch is configured to either connect or disconnect the first transmission line to the input port. The device also includes a second transmission line characterized by a second characteristic impedance and coupled between the input port and a second output port. A controller is configured to activate the first switch to set a two-output mode or to deactivate the first switch to set a one-output mode. The second characteristic impedance is configured to be the same as the first characteristic impedance at the two-output mode or configured to be reduced to 1/√{square root over (2)} of the first characteristic impedance at the one-output mode.

First claim

What is claimed is:

1 . A device comprising:
an input port configured to receive an input signal; a first output port; a second output port; a first transmission line characterized by a first characteristic impedance and coupled to the first output port; a first switch configured to either connect or disconnect the first transmission line to the input port; a second transmission line characterized by a second characteristic impedance and coupled between the input port and the second output port; and a controller configured to set a one-output mode or a two-output mode, wherein in the two-output mode, a power of the input signal is divided between the first output port and the second output port as the first switch is activated and the second characteristic impedance is configured to be equal to the first characteristic impedance; in the one-output mode, the power of the input signal is all directed to the second output port as the first switch is deactivated and the second characteristic impedance is configured to be reduced by a factor of

1

2

.

2 . The device of claim 1 , wherein each of the first output port and the second output port is associated with a load impedance.

3 . The device of claim 2 , wherein the input port is configured to receive the input signal from an analog RF source associated with a source impedance.

4 . The device of claim 1 , wherein the two-output mode supports the first output port to deliver a first output signal for cellular application and the second output port to deliver a second output signal for WiFi application.

5 . The device of claim 3 , wherein the first transmission line comprises at least two first capacitors each having a first capacitance C coupled in a serial configuration and at least one inductor having a first inductance L coupled in a shunt configuration to a node between the two capacitors, wherein the values of L and C are chosen based on conjugated impedance matching at each of the input port, the first output port, and the second output port.

6 . The device of claim 5 , wherein the second transmission line comprises at least two variable capacitors each having a second capacitance coupled in a serial configuration and at least one variable inductor having a second inductance coupled in a shunt configuration to a node between the two variable capacitors, wherein the second capacitance is configured to have a value of the first capacitance C when the first switch is activated and to change to a value of √{square root over (2C)} when the first switch is deactivated, wherein the second inductance is configured to have a value of the first inductance L when the first switch is activated and to change to L/√{square root over (2)} when the first switch is deactivated.

7 . The device of claim 6 , wherein the variable capacitor comprises a second capacitor having a third capacitance coupled in parallel to a switch-capacitor pair, the switch-capacitor pair including a second switch coupled in series with a third capacitor having a fourth capacitance.

8 . The device of claim 7 , wherein the third capacitance is equal to the first capacitance C and the fourth capacitance is equal to the first capacitance C times (√{square root over (2)}−1).

9 . The device of claim 7 , wherein the second switch is configured to connect to the third capacitor when the first switch is deactivated in the one output mode, and to disconnect from the third capacitor when the first switch is activated in the two-output mode.

10 . The device of claim 3 , further comprises a switch-resistor pair coupled between the first output port and the second output port, the switch-resistor pair comprising a third switch coupled in series to an isolation resistor, wherein the third switch is configured to be deactivated when the first switch is deactivated and to be activated when the first switch is activated.

11 . The device of claim 3 , wherein the first transmission line and the second transmission line are configured to ensure conjugated matching with the source impedance at the input port and conjugated matching with the load impedance at each of the first output port and the second output port in the two-output mode.

12 . The device of claim 3 , wherein the second transmission line is configured to ensure conjugated matching with the source impedance respectively at the input port and with the load impedance at the second output port in the one-output mode.

13 . A circuit for dividing signal power to different numbers of outputs comprising:
an input port coupled to a source associated with a source impedance; a first output port having a first load impedance; a second output port having a second load impedance equal to the first load impedance; a first transmission line configured to have a first characteristic impedance and coupled to the first output port; a first switch coupled between the input port and the first transmission line; a second transmission line configured to have a second characteristic impedance and coupled to the second output port; and a controller configured to activate or deactivate the first switch; wherein, if the first switch is activated, the first transmission line and the second transmission line are configured to have the second characteristic impedance equal to the first characteristic impedance and maintain conjugate matching with the source impedance at the input port and conjugate matching with the first load impedance at each of the first output port and the second output port; wherein, if the first switch is deactivated, the first transmission line and the second transmission line are configured to change the second characteristic impedance to

1

2

of the first characteristic impedance and maintain conjugate matching with the source impedance at the input port and conjugate matching with the first load impedance at the second output port.

14 . The circuit of claim 13 , wherein the first transmission line comprises two first capacitors each having a first capacitance C coupled in a serial configuration and at least one inductor having a first inductance L coupled in a shunt configuration to a node between the two first capacitors, wherein the values of L and C are chosen based on the conjugated impedance matching at each of the input port, the first output port, and the second output port.

15 . The circuit of claim 14 , wherein the second transmission line comprises two variable capacitors each having a second capacitance coupled in a serial configuration and at least one variable inductor having a second inductance coupled in a shunt configuration to a node between the two variable capacitors, wherein the second capacitance is configured to be equal to the first capacitance C when the first switch is activated and to vary to √{square root over (2)}C when the first switch is deactivated, wherein the second inductance is configured to be equal to the first inductance L when the first switch is activated and to vary to L/√{square root over (2)} when the first switch is deactivated.

16 . The circuit of claim 15 , wherein the variable capacitor comprises a second capacitor having a third capacitance coupled in parallel to a switch-capacitor pair, the switch-c

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Babamir Seyed Mehrdad

Classifications

• H01P5/16 Primary

  Conjugate devices, i.e. devices having at least one port decoupled from one other port · CPC title

• H03H2007/386

  Multiple band impedance matching · CPC title

• H03H2210/025

  Capacitor · CPC title

• H03H2210/026

  Inductor · CPC title

• H03H7/0123

  comprising distributed impedance elements together with lumped impedance elements · CPC title