Display device having variable stress period and method of driving the same

Patent metadata

Field	Value
Publication number	US-12475857-B2
Application number	US-202418421606-A
Country	US
Kind code	B2
Filing date	Jan 24, 2024
Priority date	Jan 30, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A display device includes: a timing controlling circuit configured to generate an image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal, a stress signal and an anode reset signal using the image data and the data control signal; a gate driving circuit configured to generate a gate 1 signal, a gate 2 signal, an emission 1 signal and an emission 2 signal using the gate control signal; and a display panel configured to display an image using the data signal, the gate 1 signal, the gate 2 signal, the emission 1 signal and the emission 2 signal, wherein a width of a stress period between a rising timing of the gate 2 signal and a rising timing of the emission 1 signal is changed according to a luminance band of the image.

First claim

What is claimed is:

1 . A display device, comprising:
a timing controlling circuit configured to generate an image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal, a stress signal, and an anode reset signal using the image data and the data control signal; a gate driving circuit configured to generate a gate 1 signal, a gate 2 signal, an emission 1 signal, and an emission 2 signal using the gate control signal; and a display panel configured to display an image using the data signal, the gate 1 signal, the gate 2 signal, the emission 1 signal and the emission 2 signal, wherein a width of a stress period between a rising timing of the gate 2 signal and a rising timing of the emission 1 signal is changed according to a luminance band of the image, and wherein the display panel includes a plurality of subpixels, each of the plurality of subpixels comprising: a storage capacitor; a first transistor switched according to the gate 2 signal, the first transistor connected to one of the data signal, the stress signal, and the anode reset signal; a second transistor switched according to a voltage of a first capacitor electrode of the storage capacitor; a third transistor switched according to the gate 1 signal, the third transistor connected to the storage capacitor and the second transistor; a fourth transistor switched according to the emission 2 signal, the fourth transistor connected to a high level signal, the second transistor, and the third transistor; a fifth transistor switched according to the emission 1 signal, the fifth transistor connected to the first transistor and the second transistor; a sixth transistor switched according to the gate 1 signal, the sixth transistor connected to the storage capacitor, the fifth transistor, and an initial voltage; and a light emitting diode connected between the fifth transistor, the sixth transistor, and a low level signal.

2 . The display device of claim 1 , wherein the display panel displays the image using one of a plurality of high level voltages according to the luminance band,
wherein the data driving circuit is configured to supply one of a plurality of parking voltages corresponding to the plurality of high level voltages during the stress period, and wherein the timing controlling circuit is configured to determine the width of the stress period according to the plurality of parking voltages.

3 . The display device of claim 1 , wherein the display panel displays the image during a plurality of frames, each of the plurality of frames comprising:
a refresh subframe where the data signal is inputted and a light corresponding to the data signal is emitted; and a holding subframe where an input of the data signal is stopped and a light corresponding to the data signal inputted during the refresh subframe is emitted.

4 . The display device of claim 3 , wherein during a first period of the refresh subframe, the data signal is applied to a gate electrode of the second transistor through the first transistor, the second transistor, and the third transistor, and the initial voltage is applied to an anode of the light emitting diode through the sixth transistor,
wherein during a second period of the refresh subframe, the stress signal is applied to a source electrode of the second transistor through the first transistor, and wherein during a third period of the refresh subframe, the high level signal is applied to the anode of the light emitting diode through the fourth transistor, the second transistor, and the fifth transistor.

5 . The display device of claim 3 , wherein during a fourth period of the holding subframe, the stress signal is applied to a source electrode of the second transistor through the first transistor,
wherein during a fifth period of the holding subframe, the anode reset signal is applied to an anode of the light emitting diode through the first transistor and the fifth transistor, and wherein during a sixth period of the holding subframe, the high level signal is applied to the anode of the light emitting diode through the fourth transistor, the second transistor and the fifth transistor.

6 . The display device of claim 1 , wherein at least one of the first transistor to the sixth transistor is an oxide semiconductor thin film transistor.

7 . The display device of claim 1 , wherein one of a plurality of luminance bands is displayed by supplying a corresponding high level voltage of a plurality of high level voltages as the high level signal to the fourth transistor, and applying one of a plurality of parking voltages that is corresponding to the corresponding high level voltage as a stress signal to a source electrode of the second transistor during the stress period.

8 . The display device of claim 7 , wherein the stress period is determined to have one of a plurality of widths according to the high level signal and the stress signal.

9 . The display device of claim 1 , wherein the gate driving circuit includes a first gate driving circuit and a second gate driving circuit disposed at both sides of the display panel;
wherein the first gate driving circuit includes a gate 1 signal circuit generating the gate 1 signal and a gate 2 signal circuit generating the gate 2 signal; and wherein the second gate driving circuit includes an emission 1 signal circuit generating the emission 1 signal and an emission 2 signal circuit generating the emission 2 signal.

10 . The display device of claim 9 , wherein the gate 1 signal circuit is disposed farther from the display panel than the gate 2 signal circuit, or the gate 2 signal circuit is disposed farther from the display panel than the gate 1 signal circuit, and
wherein the emission 1 signal circuit is disposed farther from the display panel than the emission 2 signal circuit, or the emission 2 signal circuit is disposed farther from the display panel than the emission 1 signal circuit.

11 . The display device of claim 1 , wherein the gate driving circuit includes a first gate driving circuit and a second gate driving circuit disposed at both sides of the display panel;
wherein the first gate driving circuit includes a gate 1 signal circuit generating the gate 1 signal and an emission 1 signal circuit generating the emission 1 signal; and wherein the second gate driving circuit includes a gate 2 signal circuit generating the gate 2 signal and an emission 2 signal circuit generating the emission 2 signal.

12 . The display device of claim 11 , wherein the gate 1 signal circuit is disposed farther from the display panel than the emission 1 signal circuit, or the emission 1 signal circuit is disposed farther from the display panel than the gate 1 signal circuit, and
wherein the gate 2 signal circuit is disposed farther from the display panel than the emission 2 signal circuit, or the emission 2 signal circuit is disposed farther from the display panel than the gate 2 signal circuit.

13 . The display device of claim 1 , wherein the gate driving circuit includes a first gate driving circuit and a second gate driving circuit disposed at both sides of the display panel; and
wherein each of the first gate driving circuit and the second gate driving circuit includes a gate 1 signal circuit generating the gate 1 signal, a gate 2 signal circuit generating the gate 2 signal, an emission 1 signal circuit generating the emission 1 signal and an emission 2 signal circuit generating the emission 2 signal.

14 . A method of driving a display device, comprising:
generati

Assignees

• Lg Display Co Ltd

Inventors

• Jeong Seung-Ho
• Ko Eun-Jung

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title