Gate driver and display device including the same

Patent metadata

Field	Value
Publication number	US-12475856-B2
Application number	US-202418978445-A
Country	US
Kind code	B2
Filing date	Dec 12, 2024
Priority date	Jan 17, 2024
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A gate driver includes first to n th stages. A k th stage among the first to n th stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

First claim

What is claimed is:

1 . A gate driver, comprising:
first to n th (n is a natural number greater than 2) stages, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

2 . The gate driver of claim 1 , wherein the fourth transistor is a P-type transistor.

3 . The gate driver of claim 1 , wherein a threshold voltage of the fourth transistor is negatively shifted in a period in which the first control node or the second control node of the k−1 th stage has the high gate voltage and the inverting control node of the k+1 th stage has the low gate voltage.

4 . The gate driver of claim 1 , wherein the seventh transistor is a P-type transistor.

5 . The gate driver of claim 1 , wherein the k th stage further includes
a second transistor including a gate electrically connected to the second control node, a first terminal which receives the low gate voltage, and a second terminal electrically connected to the inverting control node.

6 . The gate driver of claim 5 , wherein the k th stage further includes:
a third transistor including a gate electrically connected to the first control node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the inverting control node.

7 . The gate driver of claim 6 , wherein:
the second transistor is an N-type transistor; and the third transistor is a P-type transistor.

8 . The gate driver of claim 1 , wherein the k th stage further includes:
a first capacitor including a first terminal electrically connected to the second control node and a second terminal electrically connected to the output node; and a second capacitor including a first terminal which receives the high gate voltage and a second terminal electrically connected to the inverting control node.

9 . A gate driver, comprising:
first to n th (n is a natural number greater than 2) stages, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k−1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k+1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

10 . The gate driver of claim 9 , wherein the fourth transistor is a P-type transistor.

11 . The gate driver of claim 9 , wherein a threshold voltage of the fourth transistor is negatively shifted in a period in which the first control node or the second control node of the k+1 th stage has the high gate voltage and the inverting control node of the k−1 th stage has the low gate voltage.

12 . The gate driver of claim 9 , wherein the seventh transistor is a P-type transistor.

13 . The gate driver of claim 9 , wherein the k th stage further includes:
a second transistor including a gate electrically connected to the second control node, a first terminal which receives the low gate voltage, and a second terminal electrically connected to the inverting control node.

14 . The gate driver of claim 13 , wherein the k th stage further includes:
a third transistor including a gate electrically connected to the first control node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the inverting control node.

15 . The gate driver of claim 14 , wherein:
the second transistor is an N-type transistor; and the third transistor is a P-type transistor.

16 . The gate driver of claim 9 , wherein the k th stage further includes:
a first capacitor including a first terminal electrically connected to the second control node and a second terminal electrically connected to the output node; and a second capacitor including a first terminal which receives the high gate voltage and a second terminal electrically connected to the inverting control node.

17 . A display device, comprising:
a display panel including pixels; a data driver which provides data signals to the pixels; and a gate driver including first to n th (n is a natural number greater than 2) stages which provide first to n th gate signals to the pixels, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Cha Nahyeon
• Kim Kyungho
• No Sang Yong

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title