Driving module and display device

Patent metadata

Field	Value
Publication number	US-12475833-B2
Application number	US-202218574419-A
Country	US
Kind code	B2
Filing date	Nov 25, 2022
Priority date	Nov 25, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.

First claim

What is claimed is:

1 . A driving module, arranged in a display device, wherein the display device comprises a display panel, the display panel comprises a plurality of gate lines arranged in rows, a plurality of data lines arranged in columns and a plurality of pixel circuits arranged in rows and columns arranged in a display region; and the driving module comprises a serial-parallel conversion circuit and a data providing circuit;
the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is electrically connected to the serial-parallel conversion circuit, and is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal; wherein the serial-parallel conversion circuit comprises a serial-parallel conversion module, a mode conversion module and a common electrode voltage generation module; the serial-parallel conversion module is configured to convert the serial input signal into the parallel output signal; the mode conversion module is configured to generate the transmission control signal corresponding to a current display mode in accordance with the mode indication information carried by the parallel output signal, provide the transmission control signal and at least one bit of information in the mode indication information to the data providing circuit, and provide the mode indication information to the common electrode voltage generation module; and the common electrode voltage generation module is configured to generate a common electrode voltage, a first display control voltage and a second display control voltage corresponding to the current display mode in accordance with the mode indication information; wherein the serial-parallel conversion module comprises an N-stage shift register, N data latches or delay latches (D latches) and M control multiplexing units; the serial input signal is applied to all input ends of the N D latches; where Nis an integer greater than 1, and M is a positive integer; a chip selection signal is applied to a first input end of a first stage shift register, a system clock signal is applied to all second input ends of the N-stage shift register, an output end of the first stage shift register is electrically connected to a clock signal input end of a first D latch and a first input end of a second stage shift register, and the first stage shift register is configured to shift the chip selection signal under the control of the system clock signal to obtain a first output clock signal, and provide the first output clock signal to the clock signal input end of the first D latch; an output end of an a-th stage shift register is electrically connected to a first input end of an m-th control multiplexing unit, a second input end of the m-th control multiplexing unit is electrically connected to an output end of an N-th stage shift register, an output end of the m-th control multiplexing unit is electrically connected to a first input end of an (a+1)-th stage shift register, an m-th data bit control signal is applied to a control end of the m-th control multiplexing unit, the m-th control multiplexing unit is configured to control the output end of the a-th stage shift register or the output end of the N-th stage shift register to be connected to the first input end of the (a+1)-th stage shift register under the control of the m-th data bit control signal; the system clock signal is applied to a second input end of the (a+1)-th stage shift register, an output end of the (a+1)-th stage shift register is electrically connected to a clock signal input end of an (a+1)-th stage D latch, and the (a+1)-th stage shift register is configured to shift the signal output by the output end of the a-th stage shift register under the control of the system clock signal obtain an (a+1)-th output clock signal and provide the (a+1)-th output clock signal to the clock signal input end of the (a+1)-th stage D latch; a first input end of a b-th stage shift register is electrically connected to an output end of a (b-1)-th stage shift register, the system clock signal is applied to a second input end of the b-th stage shift register, an output end of the b-th stage shift register is electrically connected to a clock signal input end of a b-th stage D latch, and the b-th stage shift register is configured to shift the signal output from the output end of the (b-1)-th stage shift register to obtain a b-th output clock signal and provide the b-th output clock signal to the clock signal input end of the b-th stage D latch; where a is a positive integer, b is a positive integer greater than 1, and b−1 is not equal to a; m is a positive integer less than or equal to M, and M is a positive integer; and each D latch is configured to output corresponding data in the serial input signal under the control of the signal applied to the clock signal input end of the D latch.

2 . The driving module according to claim 1 , wherein the parallel output signal further carries address data, and the driving module further comprises an address processing circuit; and
the address processing circuit is electrically connected to the serial-parallel conversion circuit and is configured to process the address data to obtain row number of the pixel circuits to be operated.

3 . The driving module according to claim 2 , wherein the driving module further comprises a gate line selection circuit; the gate line selection circuit is configured to provide a gate driving signal to the gate line corresponding to the row number in accordance with the row number of the pixel circuits to be operated to control the pixel circuits corresponding to the row number to be operated.

4 . The driving module according to claim 2 , wherein the address processing circuit comprises an address latch module, an address decoding module and an address generation module;
the address latch module is configured to latch the address data carried by the parallel output signal to obtain output address data; the address decoding module is electrically connected to the address latch module and is configured to decode the output address data to obtain decoded output address data; the address generation module is configured to process the decoded output address data to obtain the row number of the pixel circuits to be operated.

5 . The driving module according to claim 1 , wherein the data providing circuit comprises a data transmission control module, a data transmission module and a data output module;
the data transmission control module is configured to receive the transmission control signal and generate a transmission control clock signal corresponding to the current display mode in accordance with the transmission control signal and the at least one bit of information in the mode indication information; the data transmission module is configured to receive the input display data from the serial-parallel conversion module and convert the input display data in accordance with the transmission control clock signal to obtain an output display data group, and the output display data group comprises at least one group of output display data; and the data output module is configured to receive the output display data group and transmit the output display data in the output display data group to the corresponding data line.

6 . The driving module according to claim 1 ,

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Shan Yue
• Wang Zhen
• Sun Jian
• Wang Deshuai
• Zhang Jian
• Yan Wei
• Qin Wenwen
• Yang Xiaoyan
• Zhang Han
• Zhang Yadong
• Han Lu

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/34

  by control of light from an independent source · CPC title