Quantum error correction decoding system and method, fault-tolerant quantum error correction system, and chip
US-11842250-B2 · Dec 12, 2023 · US
US12475403B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12475403-B2 |
| Application number | US-202318347054-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 5, 2023 |
| Priority date | Jul 14, 2022 |
| Publication date | Nov 18, 2025 |
| Grant date | Nov 18, 2025 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and communicate with the computing entity. The controller causes performance of syndrome circuit segments to generate syndromes of logical qubits. The syndrome circuit segment is performed at least partially by causing performance of a sequence of transportation operations and at-least-two-physical-qubits interactions. Each transportation operation of the sequence causes physical transport of at least one of a respective data qubit of the logical qubit or a respective ancilla qubit into a respective interaction zone defined by the quantum processor. A respective at-least-two-physical-qubits interaction is performed within the respective interaction zone. Using the syndrome, at least one quantum error correction is determined; and the controller causes a classical memory to be updated based on the syndrome and/or the quantum error correction.
Opening claim text (preview).
The invention claimed is: 1 . A method performed by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor, the controller configured to (a) control operation of the quantum processor and (b) communicate with the classical computing entity, the method comprising: causing, by the controller, performance of at least one syndrome circuit segment to generate a syndrome of a logical qubit, the at least one syndrome circuit segment performed at least in part by causing performance of a sequence of transportation operations and at-least-two- physical-qubits interactions, wherein each transportation operation of the sequence of transportation operations and at-least-two-physical-qubits interactions causes physical transport of at least one of (a) a respective data qubit of the logical qubit or (b) a respective ancilla qubit into a respective interaction zone defined by the quantum processor such that the at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancilla qubit is disposed within the respective interaction zone and a respective at-least-two-physical-qubits interaction is performed thereon; based at least in part on the syndrome of the logical qubit, determining, by the classical computing entity, at least one quantum error correction; and causing, by the controller, a classical memory of at least one of the controller or the classical computing entity to be updated based on at least one of the syndrome or the at least one quantum error correction. 2 . The method of claim 1 , further comprising causing, by the controller, the at least one quantum error correction to be applied to the logical qubit. 3 . The method of claim 1 , wherein performance of the at least one syndrome circuit segment comprises performance of a plurality of syndrome circuit segments. 4 . The method of claim 1 , wherein the logical qubit is one of a plurality of logical qubits and the respective ancilla qubit is used to perform syndrome circuit segments for two or more logical qubits of the plurality of logical qubits. 5 . The method of claim 1 , wherein the at least one syndrome circuit segment comprises a flagged syndrome circuit segment wherein a first ancilla qubit of two or more ancilla qubits used to perform the at least one syndrome circuit segment is used as flag qubit. 6 . The method of claim 1 , wherein the classical memory is updated based on at least one of the syndrome or the at least one quantum error correction comprises tracking the syndrome of the logical qubit in the classical memory. 7 . The method of claim 1 , wherein coherence of the respective data qubit of the logical qubit is maintained during performance of the at least one syndrome circuit segment. 8 . The method of claim 1 , further comprising: prior to causing performance of the at least one syndrome circuit segment, causing performance of a state preparation circuit segment for preparing a state of the respective ancilla qubit; and causing the respective ancilla qubit to be read after the performance of the sequence of transportation operations and at-least-two-physical-qubits interactions, wherein the syndrome of the logical qubit is generated based at least in part on a result of the reading of the respective ancilla qubit. 9 . The method of claim 2 , wherein causing the at least one quantum error correction to be applied to the logical qubit comprises at least one of: updating a classical qubit registry corresponding to logical qubit based on the at least one quantum error correction, causing performance of a physical correction to one or more data qubits of the logical qubit, or causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified based at least in part on the at least one quantum error correction. 10 . The method of claim 9 , wherein causing performance of the physical correction to the one or more data qubits of the logical qubit comprises performing one or more transportation operations on the one or more data qubits to cause the one or more data qubits to be transported at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor. 11 . The method of claim 3 , wherein causing performance of the at least one syndrome circuit segment comprises: causing performance of a first plurality of syndrome circuit segments, wherein the first plurality of syndrome circuit segments were selected from a defined set of syndrome circuit segments using a stochastic selection process; determining, based at least in part on respective results of the first plurality of syndrome circuit segments, whether to cause performance of a second plurality of syndrome circuit segments, the second plurality of syndrome circuit segments selected from the defined set of syndrome circuit segments; responsive to determining to cause performance of the second plurality of syndrome circuit segments, causing performance of the second plurality of syndrome circuit segments; and responsive to determining to not cause performance of the second plurality of syndrome circuit segments, determining the at least one quantum error correction based at least in part on the respective results of the first plurality of syndrome circuit segments. 12 . The method of claim 5 , further comprising: tracking, using at least one classical qubit registry, a value of the flag qubit; and causing performance of an unflagged syndrome circuit segment in response to determining that the value of the flag qubit has changed. 13 . A controller of a quantum computing system, the controller (a) configured to control operation of a quantum processor of the quantum computing system and (b) comprising a processing element and a memory storing executable instructions configured to, when executed by the processing element, cause the controller to at least: cause performance of at least one syndrome circuit segment to generate a syndrome of a logical qubit, the at least one syndrome circuit segment performed at least in part by causing performance of a sequence of transportation operations and at-least-two-physical-qubits interactions, wherein each transportation operation of the sequence of transportation operations and at-least-two-physical-qubits interactions causes physical transport of at least one of (a) a respective data qubit of the logical qubit or (b) a respective ancilla qubit into a respective interaction zone defined by the quantum processor such that the at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancilla qubit is disposed within the respective interaction zone and a respective at-least-two-physical-qubits interaction is performed thereon; cause determining of at least one quantum error correction based at least in part on the syndrome of the logical qubit; and cause a classical memory of at least one of the controller or a classical computing entity of the quantium computing system to be updated based on at least one of the syndrome or the at least one quantum error correction. 14 . The controller of claim 13 , wherein the executable instructions are further configured to, when executed by the processing element, cause the controller to at least cause the at least one quantum error correction to be applied to the logical qubit. 15 . The controller of claim 13 , wherein causing the at least one quantum error correction to be applied to the logical qubit comprises at least one of: updating a classical qubit registry corresponding to logical qubit
with specific ECC/EDC distribution · CPC title
Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title
Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.