Electromagnetic based secure contact-less integrity verification of hardware and/or software for integrated circuits

Patent metadata

Field	Value
Publication number	US-12475263-B2
Application number	US-202418589578-A
Country	US
Kind code	B2
Filing date	Feb 28, 2024
Priority date	Mar 1, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Various embodiments of the present disclosure provide electromagnetic based secure contact-less integrity verification for an integrated circuit. In one example, an embodiment provides for mapping a signal to a pseudo-random number generator (PRNG) seed value, generating a PRNG output digital signal based on the PRNG seed value, encrypting the PRNG output digital signal based on a cipher function and a key, and generating an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

First claim

The invention claimed is:

1 . A method for providing electromagnetic based secure contact-less integrity verification for an integrated circuit, the method comprising:
mapping a signal to a pseudo-random number generator (PRNG) seed value; generating a PRNG output digital signal based on the PRNG seed value; encrypting the PRNG output digital signal based on a cipher function and a key; and generating an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

2 . The method of claim 1 , further comprising:
authenticating hardware for the integrated circuit based on the non-contact sensing of the electromagnetic signal by the probing system.

3 . The method of claim 1 , further comprising:
authenticating software for the integrated circuit based on the non-contact sensing of the electromagnetic signal by the probing system.

4 . The method of claim 1 , further comprising:
applying an error correction technique to the PRNG output digital signal; and serializing the PRNG output digital signal.

5 . The method of claim 1 , further comprising:
generating the PRNG output digital signal based on a field programmable gate array (FPGA)-based linear-feedback shift register (LFSR) circuit.

6 . The method of claim 1 , further comprising:
generating the PRNG output digital signal based on a hard processor system (HPS)-based linear-feedback shift register (LFSR) circuit.

7 . The method of claim 1 , further comprising:
generating the PRNG output digital signal based on an application-specific integrated circuit (ASIC)-based linear-feedback shift register (LFSR) circuit.

8 . An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to at least:
map a signal to a pseudo-random number generator (PRNG) seed value; generate a PRNG output digital signal based on the PRNG seed value; encrypt the PRNG output digital signal based on a cipher function and a key; and generate an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

9 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
authenticate hardware for an integrated circuit based on the non-contact sensing of the electromagnetic signal by the probing system.

10 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
authenticate software for an integrated circuit based on the non-contact sensing of the electromagnetic signal by the probing system.

11 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
apply an error correction technique to the PRNG output digital signal; and serialize the PRNG output digital signal.

12 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
generate the PRNG output digital signal based on a field programmable gate array (FPGA)-based linear-feedback shift register (LFSR) circuit.

13 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
generate the PRNG output digital signal based on a hard processor system (HPS)-based linear-feedback shift register (LFSR) circuit.

14 . The apparatus of claim 8 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
generate the PRNG output digital signal based on an application-specific integrated circuit (ASIC)-based linear-feedback shift register (LFSR) circuit.

15 . A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured to:
map a signal to a pseudo-random number generator (PRNG) seed value; generate a PRNG output digital signal based on the PRNG seed value; encrypt the PRNG output digital signal based on a cipher function and a key; and generate an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

16 . The non-transitory computer storage medium of claim 15 , wherein the operations are further configured to:
authenticate an integrated circuit based on the non-contact sensing of the electromagnetic signal by the probing system.

17 . The non-transitory computer storage medium of claim 15 , wherein the operations are further configured to:
apply an error correction technique to the PRNG output digital signal; and serialize the PRNG output digital signal.

18 . The non-transitory computer storage medium of claim 15 , wherein the operations are further configured to:
generate the PRNG output digital signal based on a field programmable gate array (FPGA)-based linear-feedback shift register (LFSR) circuit.

19 . The non-transitory computer storage medium of claim 15 , wherein the operations are further configured to:
generate the PRNG output digital signal based on a hard processor system (HPS)-based linear-feedback shift register (LFSR) circuit.

20 . The non-transitory computer storage medium of claim 15 , wherein the operations are further configured to:
generate the PRNG output digital signal based on an application-specific integrated circuit (ASIC)-based linear-feedback shift register (LFSR) circuit.

Assignees

• Univ Florida
• Brookhaven Science Ass Llc

Inventors

• Bhunia Swarup
• Cruz Jonathan William
• Huan Junjun
• Mandal Soumyajit

Classifications

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F7/584

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title