Processor power management utilizing dedicated DMA engines

Patent metadata

Field	Value
Publication number	US-12474763-B2
Application number	US-202117490003-A
Country	US
Kind code	B2
Filing date	Sep 30, 2021
Priority date	Sep 30, 2021
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access (DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.

First claim

What is claimed is:

1 . A processor comprising:
a first direct memory access (DMA) engine comprising circuitry configured to transfer data between an external memory and a first partition of the processor that provides a first functionality, wherein the first partition is in a first power domain; a second direct memory access (DMA) engine comprising circuitry configured to transfer data between the external memory and a second partition of the processor, wherein the second partition is configured to provide a second functionality different from the first functionality, wherein the second partition is in a second power domain that is independent of the first power domain; and control circuitry configured to receive a task and, based on a type of the task, assign the task to either the first partition or the second partition for execution, wherein the first and second partitions operate independently and concurrently under respective power domains and respective DMA engines.

2 . The processor as recited in claim 1 , wherein responsive to a first task having a first task type, the circuitry is configured to:
transition one or more of operating parameters and control signals of the first power domain to cause the first partition to consume less power; and execute the first task by the second partition.

3 . The processor as recited in claim 2 , wherein:
the circuitry is configured to cause the second DMA engine to process the first task.

4 . The processor as recited in claim 2 , wherein:
the first task type is a non-real-time data processing task type executable by circuitry of the second partition; and the first partition comprises circuitry configured to execute a second task type, wherein the second task type is a real-time data processing task type.

5 . The processor as recited in claim 1 , wherein: functionality of the processor is included as a semiconductor die of multiple dies on a system-on-a-chip (SOC).

6 . The processor as recited in claim 4 , wherein the circuitry is further configured to:
responsive to a second task having the second task type:
transition the one or more of the operating parameters and the control signals of the first power domain to cause the first partition to consume more power; and
execute the second task by the first partition that utilizes the first DMA engine to process the second task.

7 . The processor as recited in claim 4 , wherein:
the first task type is a multimedia playback task; and the second task type is a graphics shader task.

8 . A method comprising:
responsive to a given task to be executed: causing, by a processing circuitry, a first partition of a processor to access data stored in an external memory with a first DMA engine using operating parameters of a first power domain; and executing, by the processing circuitry, using one or more functional units of the first partition, the given task using the operating parameters of the first power domain; and during execution of the given task, causing, by the processing circuitry, a second partition of the processor to access data stored in the external memory with a second DMA engine using operating parameters of a second power domain different from the first power domain.

9 . The method as recited in claim 8 , wherein responsive to the given task having a first task type, the method further comprises:
executing, by the processing circuitry, the given task using one or more functional units of the second partition using operating parameters of the second power domain; and during execution of the given task, transitioning, by the processing circuitry, one or more of the operating parameters of the first power domain to cause the first partition to consume less power.

10 . The method as recited in claim 9 , further comprising
causing, by the processing circuitry, the second DMA engine to process the given task.

11 . The method as recited in claim 9 , wherein
the first task type is a non-real-time data processing task type executable by one or more functional units of the second partition and the method further comprising causing, by the processing circuitry, the one or more functional units of the first partition to execute a second task type, wherein the second task type is a real-time data processing task type.

12 . The method as recited in claim 8 , wherein functionality of the processor is included as a semiconductor die of multiple dies on a system-on-a-chip (SOC).

13 . The method as recited in claim 11 , further comprising:
responsive to a second task having the second task type:
transitioning, by the processing circuitry, one or more of the operating parameters of the first power domain to cause the first partition to consume more power; and
executing, by the processing circuitry, the given task using the first DMA engine.

14 . The method as recited in claim 11 , wherein:
the first task type is a multimedia playback task; and the second task type is a graphics shader task.

15 . A computing system comprising:
a memory subsystem configured to store instructions of one or more tasks; and a processing circuit coupled to the memory subsystem, wherein the processing circuit comprises:
a first partition that includes a first direct memory access (DMA) engine comprising circuitry configured to transfer data between an external memory and the first partition;
a second partition that includes a second DMA engine comprising circuitry configured to transfer data between the external memory and the second partition; and
circuitry configured to:
cause the first partition to access data stored in the external memory with the first DMA engine using operating parameters of a first power domain;
execute, using one or more functional units of the first partition, a given task using the operating parameters of the first power domain; and
during execution of the given task, cause the second partition to access data stored in the external memory with the second DMA engine using operating parameters of a second power domain different from the first power domain.

16 . The computing system as recited in claim 15 , wherein responsive to the given task having a first task type, the circuitry is further configured to:
execute the given task using one or more functional units of the second partition using operating parameters of the second power domain; and during execution of the given task, transition one or more of operating parameters of the first power domain to cause the first partition to consume less power.

17 . The computing system as recited in claim 16 , wherein
the circuitry is configured to cause the second DMA engine to process the given task.

18 . The computing system as recited in claim 16 , wherein:
the first task type is a non-real-time data processing task type executable by one or more functional units of the second partition; and the one or more functional units of the first partition are configured to execute a second task type, wherein the second task type is a real-time data processing task type.

19 . The computing system as recited in claim 15 , wherein functionality of the processing circuit is included as a semiconductor die of multiple dies on a system-on-a-chip (SOC).

20 . The computing system as recited in claim 18 , wherein the circuitry is further configured to:
responsive to the given task having the second task type:
transition one or more of the operating parameters of the first power domain to cause the fir

Assignees

• Advanced Micro Devices Inc

Inventors

• Wang Ling-Ling
• Du Yuan
• Huang Zengrong
• Dong Haikun
• Shi Lingfei
• Shao Wei
• Ma Xiaojing
• Zong Qian
• Chen Shenyuan

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title