Electroluminescence display

Patent metadata

Field	Value
Publication number	US-12471441-B2
Application number	US-202217966590-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Nov 2, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

The present disclosure relates to an electroluminescence display having enhanced display quality by reducing reflection of external light. An electroluminescence display comprises: a light shielding layer on a substrate, the light shielding layer including a first metal layer and a second metal layer on the first metal layer; a first buffer layer at least partially covering the light shielding layer on the substrate; a second buffer layer on the first buffer layer; a gate insulating layer on the second buffer layer; a gate line on the gate insulating layer and non-overlapping with the light shielding layer, the gate line including a third metal layer and a fourth metal layer on the third metal layer; a passivation layer at least partially covering the gate line; a planarization layer on the passivation layer; and an emission element including a first electrode, an emission layer, and a second electrode sequentially arranged on the planarization layer.

First claim

What is claimed is:

1 . An electroluminescence display comprising:
a light shielding layer on a substrate, the light shielding layer including a first metal layer and a second metal layer on the first metal layer; a first buffer layer at least partially covering the light shielding layer on the substrate; a second buffer layer on the first buffer layer; a gate insulating layer on the second buffer layer; a gate line on the gate insulating layer and non-overlapping with the light shielding layer, the gate line including a third metal layer and a fourth metal layer on the third metal layer; a passivation layer at least partially covering the gate line; a planarization layer on the passivation layer; and an emission element including a first electrode, an emission layer, and a second electrode sequentially arranged on the planarization layer, wherein the second electrode includes:
a first cathode layer on the emission layer;
a second cathode layer on the first cathode layer; and
a third cathode layer on the second cathode layer.

2 . The electroluminescence display of claim 1 , further comprising:
a bank covering circumference areas of the first electrode and exposing portions of the first electrode to define an emission area, the bank including black resin material.

3 . The electroluminescence display of claim 1 , wherein the second cathode layer has a thickness such that a first reflected light reflected from a bottom surface of the first cathode layer has a first phase and a second reflected light reflected from the third cathode layer has a second phase that is opposite the first phase.

4 . The electroluminescence display of claim 3 , wherein the first cathode layer comprises a first metal material and a first thickness in a range of 100 Å to 200 Å,
wherein the second cathode layer comprises a conductive organic material including a domain material and a dopant, and
wherein the third cathode layer comprises a second metal material and a second thickness in a range of 2,000 Å to 4,000 Å.

5 . The electroluminescence display of claim 1 , wherein the first metal layer comprises a thickness such that a first reflected light reflected from a bottom surface of the first metal layer has a first phase and a second reflected light reflected at an interface between the first metal layer and the second metal layer has a second phase that is opposite the first phase.

6 . The electroluminescence display of claim 5 , wherein the first metal layer and the third metal layer each comprise a metal oxide material and a thickness in a range of 100 Å to 500 Å, and
wherein the second metal layer and the fourth metal layer each comprise a metal material and a thickness in a range of 2,000 Å to 4,000 Å.

7 . The electroluminescence display of claim 1 , wherein the first buffer layer comprises a first refractive index, and the second buffer layer comprises a second refractive index that is different from the first refractive index.

8 . The electroluminescence display of claim 7 , wherein the substrate, the gate insulating layer, and the passivation layer comprise the second refractive index.

9 . The electroluminescence display of claim 7 , wherein the first buffer layer comprises silicon nitride having a first refractive index of 1.8, and
wherein the second buffer layer comprises a silicon oxide having a second refractive index of 1.5.

10 . The electroluminescence display of claim 1 , wherein the first buffer layer comprises a thickness such that a first reflected light reflected from a first interface between the substrate and the first buffer layer has a first phase and a second reflected light reflected from a second interface between the first buffer layer and the second buffer layer has a second phase that is opposite the first phase.

11 . The electroluminescence display of claim 10 , wherein the first buffer layer comprises a silicon nitride having a first thickness in a range of 1,300 Å to 1,700 Å, and
wherein the second buffer layer comprises a silicon oxide having a second thickness in a range of 2,000 Å to 2,400 Å.

12 . The electroluminescence display of claim 1 , further comprising:
a semiconductor layer disposed on the second buffer layer, the semiconductor layer overlapped with the light shielding layer and at least partially covered by the gate insulating layer; a gate electrode, a source electrode, and a drain electrode on the gate insulating layer, the gate electrode comprising at least one of the third metal layer and the fourth metal layer included in the gate line, wherein the source electrode is in contact with a first portion of the semiconductor layer, the drain electrode is in contact with a second portion of the semiconductor layer, and the gate electrode is overlapped with a third portion of the semiconductor layer that is between the first portion of the semiconductor layer and the second portion of the semiconductor layer.

13 . The electroluminescence display of claim 12 , wherein the light shielding layer includes:
a light shielding area overlapping the semiconductor layer; and a line area that is separated from the light shielding area, the line area including at least one of a data line and a driving current line.

14 . The electroluminescence display of claim 1 , wherein the first metal layer and the third metal layer comprise molybdenum-titanium-oxide, and each of the second metal layer and the fourth metal layer include at least one of copper, aluminum, silver, and gold.

15 . An electroluminescence display comprising:
a light shielding layer on a substrate, the light shielding layer including a plurality of first reflective layers, wherein light reflected by each of the plurality of first reflective layers have opposite phases such that the light reflected by the plurality of first reflective layers at least partially destructively interfere; a plurality of buffer layers on the light shielding layer; a gate insulating layer on the plurality of buffer layers; a gate line on the gate insulating layer and non-overlapping with the light shielding layer, the gate line including a plurality of second reflective layers, wherein light reflected by each of the plurality of second reflective layers have opposite phases such that the light reflected by the plurality of second reflective layers at least partially destructively interfere; a passivation layer at least partially covering the gate line; a planarization layer on the passivation layer; and an emission element including a first electrode, an emission layer, and a second electrode sequentially arranged on the planarization layer, wherein the second electrode includes a plurality of cathode layers including:
a first cathode layer on the emission layer;
a second cathode layer on the first cathode layer; and
a third cathode layer on the second cathode layer.

16 . The electroluminescence display of claim 15 , wherein
the first cathode layer includes a first metal material and a first thickness in a range of 100 Å to 200 Å; the second cathode layer includes a conductive organic material comprising a domain material and a dopant; and the third cathode layer includes a second metal material and a second thickness in a range of 2,000 Å to 4,000 Å.

17 . The electroluminescence display of claim 15 , wherein the plurality of first reflective layers includes a first metal layer and a second metal layer, and the plurality of second reflective layers includes a third metal layer and a fourth metal layer,
wherein the first metal layer and the third m

Assignees

• Lg Display Co Ltd

Inventors

• Ahn Jiyoung
• Kim Yongjae

Classifications

• H10K2102/00

  Constructional details relating to the organic devices covered by this subclass · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K50/858

  comprising refractive means, e.g. lenses · CPC title

• H10K50/856

  comprising reflective means · CPC title

• H10K59/8791 Primary

  Arrangements for improving contrast, e.g. preventing reflection of ambient light · CPC title