Array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12471376-B2
Application number	US-202218043304-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Jun 22, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

First claim

What is claimed is:

1 . An array substrate, comprising a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines;
wherein a respective first reset signal line of the plurality of first reset signal lines is connected to a row of first connecting lines of the plurality of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively; the plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network; a respective second reset signal line of the plurality of second reset signal lines is connected to one or more of the plurality of third reset signal lines; a respective third reset signal line of the plurality of third reset signal lines is connected to one or more of the plurality of second reset signal lines; the plurality of second reset signal lines respectively cross over the plurality of third reset signal lines; and the respective third reset signal line is connected to source electrodes of second reset transistors in a column of subpixels.

2 . The array substrate of claim 1 , wherein voltage levels of the plurality of first reset signals and the plurality of second reset signals are different from each other.

3 . The array substrate of claim 1 , comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises an N 1 node connected to a gate electrode of a driving transistor and an N 4 node connected to a drain electrode of a light emitting control transistor; and reset voltage levels at the N 1 node and the N 4 node are different from each other.

4 . The array substrate of claim 1 , comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein the plurality of first reset signal lines, the plurality of second reset signal lines are in a second conductive layer comprising second capacitor electrodes of storage capacitors of the plurality of pixel driving circuits; and the plurality of third reset signal lines and the plurality of first connecting lines are in a first signal line layer comprising a plurality of voltage supply lines.

5 . The array substrate of claim 1 , wherein a respective third reset signal line of the plurality of third reset signal lines comprises a main line with an overall extension direction along a second direction, and a branch line connected to and extending away from the main line; and
the branch line extends along a direction substantially parallel to a first direction.

6 . The array substrate of claim 5 , wherein an orthographic projection of the branch line on a base substrate is between an orthographic projection of a respective reset control signal line of a plurality of reset control signal lines on the base substrate and an orthographic projection of an interference preventing block on the base substrate, and between an orthographic projection of the main line on the base substrate and an orthographic projection of a respective voltage supply line of a plurality of voltage supply lines on the base substrate.

7 . The array substrate of claim 5 , wherein an orthographic projection of the branch line on a base substrate is non-overlapping with an orthographic projection of any signal line in a first conductive layer on the base substrate, is non-overlapping with an orthographic projection of any signal line in a second conductive layer on the base substrate, and is non-overlapping with an orthographic projection of any signal line in a second signal line layer on the base substrate.

8 . The array substrate of claim 1 , wherein a respective third reset signal line of the plurality of third reset signal lines comprises a first portion extending along a direction substantially parallel to a first direction, and a second portion extending along a direction substantially parallel to a second direction;
an orthographic projection of the first portion on a base substrate at least partially overlaps with an orthographic projection of a respective second reset signal line of a present stage on the base substrate; and an orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a gate protrusion of a respective gate line of a plurality of gate lines on the base substrate.

9 . The array substrate of claim 1 , wherein a respective third reset signal line of the plurality of third reset signal lines comprises a third portion extending along a direction substantially parallel to a first direction, and a fourth portion extending along a direction substantially parallel to a second direction;
an orthographic projection of the third portion on a base substrate at least partially overlaps with an orthographic projection of a respective second reset signal line of a present stage of the plurality of second reset signal lines on the base substrate, and at least partially overlaps with an orthographic projection of a respective reset control signal line in the present stage of a plurality of reset control signal lines on the base substrate; and an orthographic projection of the fourth portion on the base substrate at least partially overlaps with an orthographic projection of a gate protrusion of a respective gate line of a plurality of gate lines on the base substrate.

10 . The array substrate of claim 1 , comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises at least one transistor, which includes a source electrode, a drain electrode, and an active layer having a channel part; and the active layer further comprises at least one of a first lightly doped drain region between the channel part and the source electrode, or a second lightly doped drain region between the channel part and the drain electrode.

11 . The array substrate of claim 10 , wherein the at least one transistor having lightly doped drain region is a reset transistor.

12 . The array substrate of claim 10 , wherein the at least one transistor having lightly doped drain region is a reset transistor having a drain electrode connected to an N 1 node; and
the N 1 node is a node connected to a gate electrode of a driving transistor, and connected to a first capacitor electrode of a storage capacitor.

13 . The array substrate of claim 10 , wherein the at least one transistor having lightly doped drain region is a reset transistor having a drain electrode connected to an N 3 node; and
the N 3 node is a node connected to a drain electrode of a driving transistor and a source electrode of a light emitting control transistor.

14 . The array substrate of claim 10 , wherein the at least one transistor having lightly doped drain region is a compensation transistor configured to provide a compensation voltage signal to a gate electrode of a driving transistor;
a source electrode of the compensation transistor is connected an N 1 node; a drain electrode of the compensation transistor is connected to an N 3 node; the N 1 node is a node connected to a gate electrode of a driving transistor, and connected to a first capacitor elect

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhang Tiaomei
• Qing Haigang
• Song Gukhwan
• Yu Ziyang
• Xiao Yunsheng
• Gu Quanyong
• Wang Mengqi
• Li Zhengkun
• Li De
• Yi Hong
• Chen Wenbo
• Yang Zhongliu
• Wang Shilong
• Zhao Pan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title