Back plate and anode back plate for 3D printing

Patent metadata

Field	Value
Publication number	US-12471372-B2
Application number	US-202117770590-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Sep 25, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A back plate includes a base substrate, gate lines, data lines and power supply lines arranged on the base substrate crossing each other in rows and columns, and pixel structures arranged in an array on the base substrate, each pixel structure includes a driving transistor, a switching transistor connected thereto, and a pixel electrode connected thereto; a gate line and a data line are connected to the switching transistor, and a power supply line is connected to the driving transistor; in a same row or column of pixel structures, a power supply line is arranged between an (2n−1)th pixel structure and an 2n-th pixel structure, and the power supply line is connected to a source electrode of a driving transistor in the (2n−1)th pixel structure and a source electrode of a driving transistor in the 2n-th pixel structure; n is a positive integer greater than or equal to 1.

First claim

What is claimed is:

1 . A back plate, comprising a base substrate, gate lines, data lines and power supply lines arranged on the base substrate crossing each other in rows and columns, and pixel structures arranged in an array on the base substrate, wherein
each pixel structure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor; a gate line and a data line are connected to the switching transistor, and a power supply line is connected to the driving transistor; in a same row of pixel structures or a same column of pixel structures, a power supply line is arranged between an (2n−1)th pixel structure and an 2n-th pixel structure, and the power supply line is connected to a source electrode of a driving transistor in the (2n−1)th pixel structure and a source electrode of a driving transistor in the 2n-th pixel structure; n is a positive integer greater than or equal to 1; wherein, in a pixel area where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction, a gate electrode of the driving transistor extends in the row direction from the data line to the power supply line, and the gate electrode of the driving transistor extends in the column direction from the gate line of a previous row of pixel structures to the switching transistor; a width direction of a channel in an active layer pattern of the driving transistor is consistent with the row direction, and the channel extends in the row direction from the data line arranged on one side of the pixel structure to the power supply line arranged on the other side of the pixel structure; the gate electrode of the driving transistor is connected to a drain electrode of the switching transistor, the source electrode of the driving transistor is electrically connected to the power supply line, and the drain electrode of the driving transistor is electrically connected to the pixel electrode; a source electrode of the switching transistor is electrically connected to the data line, and a gate electrode of the switching transistor is electrically connected to a gate line; wherein a length of the gate electrode of the driving transistor in the column direction is greater than a length of the active layer pattern of the driving transistor in the column direction, so that the gate electrode of the driving transistor extends towards the switching transistor relative to the active layer thereby forming an extension portion of the gate electrode of the driving transistor, and orthographic projections of the extension portion of the gate electrode and the active layer pattern of the driving transistor on the base substrate are non-overlapping with each other; the drain electrode of the driving transistor is electrically connected to the pixel electrode through a capacitor electrode layer; orthographic projections of the capacitor electrode layer and the extension portion on the base substrate at least partially overlap with each other, and the capacitor electrode layer at least forms a capacitance with the extension portion of the gate electrode.

2 . The back plate according to claim 1 , wherein the driving transistor in the (2n−1)th pixel structure is a first driving transistor, and the driving transistor in the 2n-th pixel structure is a second driving transistor;
the power supply line and a source electrode of the first driving transistor are located on different layers, the power supply line and a source electrode of the second driving transistor are located on different layers, and the power supply line is connected to the source electrode of the first driving transistor and the source electrode of the second driving transistor through a via hole.

3 . The back plate according to claim 2 , wherein the source electrode of the first driving transistor and the source electrode of the second driving transistor are located on a same layer, the source electrode of the first driving transistor is connected to the source electrode of the second driving transistor, and a position where the power supply line and the source electrode are connected through the via hole is a position where the source electrode of the first driving transistor and the source electrode of the second driving transistor are connected.

4 . The back plate according to claim 1 , wherein the gate lines extend along a row direction of the array, and the data lines and the power supply lines extend along a column direction of the array; two data lines respectively connected to a switching transistor in the 2n-th pixel structure and a switching transistor in a (2n+1)th pixel structure are arranged between the 2n-th pixel structure and the (2n+1)th pixel structure, two data lines respectively connected to a switching transistor in the (2n−1)th pixel structure and a switching transistor in a (2n−2)th pixel structure are arranged between the (2n−1)th pixel structure and the (2n−2)th pixel structure.

5 . The back plate according to claim 1 , wherein the gate line has a first protruding portion, the data line has a second protruding portion, the gate electrode of the switching transistor is the first protruding portion, and the source electrode of the switching transistor is the second protruding portion; a width direction of a channel of an active layer pattern of the switching transistor is perpendicular to the width direction of the channel of the driving transistor;
the switching transistor further includes an extension portion connected to the drain electrode, the extension portion extends from the switching transistor to the power supply line, and the drain electrode of the switching transistor is connected to the gate electrode of the driving transistor through the extension portion.

6 . The back plate according to claim 1 , wherein the pixel electrode is an anode;
the gate line extends along the row direction of the array and is located on a side of the pixel structure close to a next row of pixel structures; the data lines extends along the column direction of the array, the power supply line includes a power supply line extending along the column direction; the data line and the power supply line extending along the column direction are located on opposite sides of the pixel structure; in a pixel area where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction; a gate electrode of the driving transistor extends in the row direction from the data line to the power supply line, and the gate electrode of the driving transistor extends in the column direction from the gate line of a previous row of pixel structures to the switching transistor; a width direction of a channel in an active layer pattern of the driving transistor is the row direction, and the channel extends in the row direction from the data line located on one side of the pixel structure to the power supply line located on the other side of the pixel structure; a gate electrode of the driving transistor is connected to a drain electrode of the switching transistor, the source electrode of the driving transistor is electrically connected to the power supply line, and the drain electrode of the driving transistor is electrically connected to the pixel electrode; a source electrode of the switching transistor is electrically connected to the data line, and a gate electrode of the switching transistor is electrically connected to the gate line; wherein the gate line has a first protruding portion, and the data line has a second protruding portion; a width direction of a channel of an active layer pattern of the switching transistor is perpendicular to the width dir

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Guo Yitong
• Zhou Jian
• Sun tuo
• Xu Xiaochun

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title