Apparatus for receiving data from memory

Patent metadata

Field	Value
Publication number	US-12470439-B2
Application number	US-202318506544-A
Country	US
Kind code	B2
Filing date	Nov 10, 2023
Priority date	Nov 11, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.

First claim

What is claimed is:

1 . An apparatus for receiving data from memory, which is configured to receive a data signal and a clock signal output from the memory, comprising:
a Decision Feedback Equalizer (DFE) including two or more differential signal path circuits configured to determine and output an output value corresponding to the data signal, wherein: each of the two or more differential signal path circuits determines a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path circuits in such a way that the two or more differential signal path circuits operate at different clocks, and includes an offset control circuit configured to adjust an offset at an input stage including at least one transistor and a feedback control circuit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path circuits.

2 . The apparatus of claim 1 , wherein each of the two or more differential signal path circuits includes
a summer configured to amplify a difference between the data signal and a reference voltage based on the previous output value fed back from the different one of the two or more differential signal path circuits; and a latch configured to set an output value to ‘1’ or ‘0’ based on the difference between the data signal and a reference signal, which is output from the summer, and to output the output value.

3 . The apparatus of claim 2 , wherein each of the two or more differential signal path circuits further includes an set-reset (SR) latch configured to hold a signal output from the latch.

4 . The apparatus of claim 2 , wherein the summer includes
a first transistor configured to receive the data signal; a second transistor configured to receive the reference voltage; a first offset control circuit connected to the first transistor and configured to adjust a voltage of the first transistor depending on an applied offset control signal; and a second offset control circuit connected to the second transistor and configured to adjust a voltage of the second transistor depending on an applied control signal.

5 . The apparatus of claim 4 , wherein each of the first offset control circuit and the second offset control circuit is a transistor array.

6 . The apparatus of claim 4 , wherein:
the first offset control circuit includes a third transistor configured to receive the data signal and a fourth transistor connected in series to the third transistor and configured to receive the offset control signal, and at least one of a pair of the third transistor and the fourth transistor is connected in parallel to the first transistor.

7 . The apparatus of claim 4 , wherein:
the second offset control circuit includes a fifth transistor configured to receive the reference voltage and a sixth transistor connected in series to the fifth transistor and configured to receive the offset control signal from outside, and at least one of a pair of the fifth transistor and the sixth transistor is connected in parallel to the second transistor.

8 . The apparatus of claim 2 , wherein the summer includes the feedback control circuit that is used as the load of the output stage and changed by the previous output value fed back from the different one of the two or more differential signal path circuits.

9 . The apparatus of claim 8 , wherein:
the feedback control circuit is configured with multiple transistors, and part of the multiple transistors are selectively turned on depending on an applied DFE control signal, thereby adjusting a magnitude of the previous output value fed back from the different one of the two or more differential signal path circuits.

10 . A summer for amplifying and outputting a difference between a data signal and a reference voltage input thereto, comprising:
an offset control circuit configured to adjust an offset at an input stage including a first transistor configured to receive a clock signal, a second transistor configured to receive the data signal, a third transistor configured to receive the reference voltage input, wherein the offset control circuit includes:
a first offset transistor array configured to adjust a voltage of the second transistor using a first pair of series-connected transistors, based on a first offset control signal; and
a second offset transistor array configured to adjust a voltage of the third transistor, based on a second offset control signal; and
a feedback control circuit configured to change a load of an output stage using a digital decision output value corresponding to a previous data signal that is fed back.

11 . The summer of claim 10 , wherein the first offset transistor array is further configured to adjust the voltage of the second transistor using a first pair of series-connected transistors, based on the data signal and the first offset control signal that are applied to different transistors within the first pair, respectively, and
the second offset transistor array is further configured to adjust the voltage of the third transistor using a second pair of series-connected transistors, based on the reference voltage input and the second offset control signal that are applied to different transistors within the second pair, respectively.

12 . The summer of claim 10 , wherein:
the first offset transistor array includes a fourth transistor configured to receive the data signal and a fifth transistor connected in series to the fourth transistor and configured to receive the first offset control signal, and at least one of a pair of the fourth transistor and the fifth transistor is connected in parallel to the second transistor.

13 . The summer of claim 10 , wherein:
a second offset control circuit includes a sixth transistor configured to receive the reference voltage and a seventh transistor connected in series to the sixth transistor and configured to receive the second offset control signal from outside, and at least one of a pair of the sixth transistor and the seventh transistor is connected in parallel to the third transistor.

14 . The summer of claim 10 , wherein:
the feedback control circuit is configured with multiple transistors, and part of the multiple transistors are selectively turned on depending on an applied Decision Feedback Equalizer (DFE) control signal, thereby adjusting a magnitude of the previous data signal that is fed back.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Jeon Young-Deuk
• Kwon Young-Su
• Kim Yi-Gyeong
• Park Su-Jin
• Cho Min-Hyung
• Choi Jae-Woong

Classifications

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F2213/16

  Memory access · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title