Programmable application-specific array for protecting confidentiality and integrity of hardware IPS

Patent metadata

Field	Value
Publication number	US-12470221-B2
Application number	US-202217808179-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Jun 30, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A method and system are directed to protecting hardware IP, particularly of ASIC designs. Programmability is introduced into an ASIC design to increase the difficulty of formulating ASIC designs as Boolean Satisfiability (SAT) problems. Fine-grain redaction of security-critical information from a design is employed by removing high-entropy logic blocks and subsequently inserting programmable components in place of the redacted portion to hide the actual design intent.

First claim

What is claimed is:

1 . A method of protecting an integrated circuit design against confidentiality and integrity attacks, the method comprising:
receiving, by a computing device, a file including data comprising a hardware netlist; converting, by the computing device, the data into a hypergraph, wherein the hypergraph comprises (i) a plurality of nodes representative of a plurality of logic gates and (ii) one or more edges representative of one or more connections of the plurality of logic gates; replacing, by the computing device, a node from the plurality of nodes in the hypergraph with a configurable lookup table (LUT); inserting, by the computing device, a first programmable component into the hypergraph based on the configurable LUT, wherein the first programmable component comprises a programmable interconnect that is inserted at an output of the configurable LUT; and generating, by the computing device, a redacted design output file based on the hypergraph including the configurable LUT and the first programmable component.

2 . The method of claim 1 wherein the hypergraph comprises a directed acyclic graph comprising one or more of an AND gate, an OR gate, or an inverter gate.

3 . The method of claim 1 further comprising identifying a security critical node from the plurality of nodes based on a cost of removal corresponding to the security critical node.

4 . The method of claim 3 further comprising calculating, for the plurality of nodes in the hypergraph, a cost function using stochastic properties comprising Shannon entropy E, fan-in cone FI, or fan-out cone FO.

5 . The method of claim 3 further comprising:
determining, for the security critical node, a maximum fan-out free cone (MFFC);
obtaining a local optimal cut by analyzing the MFFC based on area and delay; and
selecting a globally optimal cut from the local optimal cut based on normalized area and delay cost of the local optimal cut based on a pre-defined security target.

6 . The method of claim 5 further comprising:
mapping the globally optimal cut to the configurable LUT according to size; and
chaining the configurable LUT based on order of a proximity metric that is calculated from a relative distance of the plurality of logic gates corresponding to the node.

7 . The method of claim 1 further comprising connecting a second programmable component to an input of the programmable interconnect at a same logic depth as the configurable LUT.

8 . The method of claim 7 wherein the second programmable component comprises at least one of a programmable flip-flop (FF) or a programmable clock gating.

9 . The method of claim 1 wherein the programmable interconnect comprises a XOR gate or a XNOR gate and one or more multiplexers (MUXes).

10 . The method of claim 1 further comprising:
identifying, from the hypergraph, one or more logic cones that store critical information; and
mapping the one or more logic cones to a M×N configurable LUT using Shannon Decomposition Theorem or Boole's Expansion Theorem.

11 . The method of claim 1 further comprising:
generating a configuration bitstream for the configurable LUT by simulating logic corresponding to the node.

12 . The method of claim 11 wherein the configurable LUT is programmed using the configuration bitstream.

13 . The method of claim 11 wherein the configuration bitstream is stored in one or more shift registers of varying sizes.

14 . The method of claim 13 wherein a shift register of the one or more shift registers comprises a plurality of latches, wherein a latch from the plurality of latches comprises an enable pin.

15 . The method of claim 11 further comprising loading the configuration bitstream to a daisy-chained shift register, wherein (i) the daisy-chained shift register comprises a latch-based configuration, (ii) the latch-based configuration comprises a plurality of latches and a finite-state machine-based controller, and (iii) the finite-state machine-based controller is configured to generate enable signals for the plurality of latches.

16 . The method of claim 11 wherein one or more bits of the configuration bitstream are shared between a plurality MUXes within the configurable LUT or in between the configurable LUT.

17 . The method of claim 1 further comprising replacing one or more nodes in the hypergraph corresponding to one or more flip-flops in a shift register with one or more scan-based FFs.

18 . The method of claim 17 wherein the one or more scan-based FFs are controllable via a scan enable signal to select between a configuration bit functionality or a design FF functionality.

19 . The method of claim 17 further comprising:
connecting the one or more scan-based FFs to one or more inputs of a MUX in a MUX array; and
coupling an output of the configurable LUT to a field-programmable gate array-like block.

Assignees

• Univ Florida
• Intel Corp

Inventors

• Bhunia Swarup
• Dasgupta Aritra
• Gaikwad Pravin
• Rahman Md Moshiur
• Bhattacharyay Aritra
• Dorairaj Nij
• Kehlet David

Classifications

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• G06F9/4498

  Finite state machines · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title