Buck-boost boot refresher circuit

Patent metadata

Field	Value
Publication number	US-12470144-B2
Application number	US-202318155407-A
Country	US
Kind code	B2
Filing date	Jan 17, 2023
Priority date	Feb 3, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

In accordance with an embodiment, a method of operating a buck-boost power supply includes operating the buck-boost power supply in a buck mode by providing a PWM signal to a first half-bridge circuit, and turning on a charge transfer switch coupled between a first boosted supply node of a second driver circuit coupled to the first half-bridge circuit and a second boosted supply node of a second driver circuit coupled to a second half-bridge circuit when a voltage between the second boosted supply node and an output of the second half-bridge circuit is below a first threshold; and operating the buck-boost power supply in a boost mode by providing a PWM signal to the second half-bridge circuit, and turning on the charge transfer switch when the voltage between the first boosted supply node and an output of the first half-bridge circuit is below a second threshold.

First claim

What is claimed is:

1 . A buck-boost converter circuit, including:
a first half-bridge circuit arranged between an input node configured to receive an input voltage and a ground node, the first half-bridge circuit including a first high-side switch arranged between the input node and a first switching node, and a first low-side switch arranged between the first switching node and the ground node; a second half-bridge circuit arranged between an output node configured to provide an output voltage and the ground node, the second half-bridge circuit including a second high-side switch arranged between the output node and a second switching node, and a second low-side switch arranged between the second switching node and the ground node; a control circuit configured to receive a first control signal indicative, when asserted, of the buck-boost converter circuit operating in a buck mode and a second control signal indicative, when asserted, of the buck-boost converter circuit operating in a boost mode, the control circuit being further configured to produce a buck pulse-width modulated control signal and a boost pulse-width modulated control signal; a first high-side driver circuit configured to receive the buck pulse-width modulated control signal and drive the first high-side switch as a function thereof, the first high-side driver circuit being biased between a first high-side supply voltage node and the first switching node; a second high-side driver circuit configured to receive the boost pulse-width modulated control signal and drive the second high-side switch as a function thereof, the second high-side driver circuit being biased between a second high-side supply voltage node and the second switching node; a first bootstrap circuit configured to be selectively conductive from a reference voltage node towards the first high-side supply voltage node; a second bootstrap circuit configured to be selectively conductive from the reference voltage node towards the second high-side supply voltage node; a first voltage sensing circuit configured to sense a first voltage between the first high-side supply voltage node and the first switching node, and to assert a first activation signal in response to the sensed first voltage being lower than a first threshold; a second voltage sensing circuit configured to sense a second voltage between the second high-side supply voltage node and the second switching node, and to assert a second activation signal in response to the sensed second voltage being lower than a second threshold; at least one charge transfer switch directly connected between the first high-side supply voltage node and the second high-side supply voltage node; and bootstrap refresher control circuitry configured to close the at least one charge transfer switch in response to:
the first control signal being asserted, the first high-side switch being conductive and the second activation signal being asserted, or
the second control signal being asserted, the second high-side switch being conductive and the first activation signal being asserted;
wherein the at least one charge transfer switch includes at least one switch having a selectable resistance value, and wherein the bootstrap refresher control circuitry is further configured to:
determine a voltage difference between the first high-side supply voltage node and the second high-side supply voltage node, and
set a resistance value of the at least one charge transfer switch as a function of the determined voltage difference, wherein a higher resistance value of the at least one charge transfer switch is set in response to a higher value of the determined voltage difference.

2 . The buck-boost converter circuit of claim 1 , wherein the first high-side switch, the first low-side switch, the second high-side switch and the second low-side switch include n-channel MOS transistors.

3 . The buck-boost converter circuit of claim 1 , wherein the at least one charge transfer switch includes at least one p-channel MOS transistor.

4 . The buck-boost converter circuit of claim 1 , wherein the at least one charge transfer switch includes a first charge transfer switch directly connected between the first high-side supply voltage node and an intermediate node of a charge transfer path, and a second charge transfer switch directly connected between the second high-side supply voltage node and the intermediate node of the charge transfer path.

5 . The buck-boost converter circuit of claim 1 , wherein the at least one charge transfer switch includes a plurality of selectively activatable switches connected in parallel, and wherein the bootstrap refresher control circuitry is configured to produce respective control signals for activating the selectively activatable switches connected in parallel as a function of the determined voltage difference, wherein fewer switches connected in parallel are activated in response to an increased value of the determined voltage difference.

6 . The buck-boost converter circuit of claim 1 , wherein the bootstrap refresher control circuitry is configured to determine the voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a difference between the input voltage and the output voltage.

7 . The buck-boost converter circuit of claim 1 , wherein the bootstrap refresher control circuitry is configured to determine the voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a function of the output voltage and at least one of a duty-cycle of the buck pulse-width modulated control signal or a duty-cycle of the boost pulse-width modulated control signal.

8 . The buck-boost converter circuit of claim 1 , wherein:
the first voltage sensing circuit includes:
a first voltage-to-current converter circuit configured to produce a first output current indicative of the first voltage between the first high-side supply voltage node and the first switching node,
a first resistance coupled to a ground node and arranged to receive the first output current to produce a first voltage signal indicative of the first voltage between the first high-side supply voltage node and the first switching node, and
a first comparator configured to compare the first voltage signal to the first threshold and assert the first activation signal in response to the first voltage signal being lower than the first threshold; and
the second voltage sensing circuit includes:
a second voltage-to-current converter circuit configured to produce a second output current indicative of the second voltage between the second high-side supply voltage node ( 117 ) and the second switching node,
a second resistance coupled to the ground node and arranged to receive the second output current to produce a second voltage signal indicative of the second voltage between the second high-side supply voltage node and the second switching node, and
a second comparator configured to compare the second voltage signal to the second threshold and assert the second activation signal in response to the second voltage signal being lower than the second threshold.

9 . The buck-boost converter circuit of claim 1 , wherein:
the first bootstrap circuit includes a semiconductor junction having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the first high-side supply voltage node; and the second bootstrap circuit includes a semiconductor junction having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the second high-side supply voltage node.

10 . The buck-boost converter circuit

Assignees

• St Microelectronics Srl

Inventors

• Guerra Ranieri
• Grasso Leandro
• Versace Serena Angela
• Mignemi Francesca Giacoma
• Greco Nunzio

Classifications

• H02M3/157

  with digital control · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M1/36

  Means for starting or stopping converters · CPC title