Inductor flux control circuits

Patent metadata

Field	Value
Publication number	US-12470141-B2
Application number	US-202218065552-A
Country	US
Kind code	B2
Filing date	Dec 13, 2022
Priority date	Mar 2, 2015
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) prefluxing the inductor then charging the capacitor causing an increased current to flow in the inductor and (2) prefluxing the inductor then discharging the capacitor causing increased current to flow in the inductor. The inductor prefluxing steps enable the circuit to provide increased output voltage and/or increased output current.

First claim

What is claimed is:

1 . A flux control circuit for an inductor comprising:
a capacitor bank having a plurality of capacitors; a fixed current source arranged to supply a fixed level of current to the capacitor bank; a variable current source controlled by a variable feedback signal that is an output of a preflux tuning algorithm and arranged to supply a variable level of current to the capacitor bank, and wherein the capacitor bank is directly coupled to the fixed and variable current sources; and a controller having a variable timer, wherein the controller is arranged to control supplying a current to the inductor for a duration of time that is controlled by the variable timer, and wherein the variable timer controls the supplying of the variable level of current by the variable current source to the capacitor bank.

2 . The flux control circuit of claim 1 , wherein the capacitor bank is a switched capacitor bank and is arranged to be programmed to activate a specific number of capacitors using most significant bits (MSB) of a digital to analog conversion (DAC) code that represents a target voltage at an output terminal of the inductor.

3 . The flux control circuit of claim 1 , wherein the controller comprises a sample and hold circuit having a set point that is substantially equal to a voltage at an output terminal of the inductor.

4 . The flux control circuit of claim 3 , wherein the sample and hold circuit is coupled to a comparator.

5 . The flux control circuit of claim 4 , wherein the sample and hold circuit is arranged to sample an output voltage of the capacitor bank, and wherein the comparator is arranged to receive the sampled output voltage of the capacitor bank and compare it to the voltage at the output terminal of the inductor.

6 . The flux control circuit of claim 5 , wherein the sample and hold circuit and the comparator, in combination, are arranged to stop supplying current to the inductor when the output voltage of the capacitor bank is equal to the voltage at the output terminal of the inductor.

7 . A method of controlling flux for an inductor, the method comprising:
providing a capacitor bank having a plurality of capacitors; supplying, by a fixed current source, a fixed level of current to the capacitor bank; supplying, by a variable current source, a variable level of current to the capacitor bank, wherein the variable current source is controlled by a variable feedback signal that is an output of a preflux tuning algorithm and directly coupled to the fixed and variable current sources; and controlling, by a controller having a variable timer, supplying of a current to the inductor for a duration of time that is controlled by the variable timer, wherein the variable timer controls the supplying of the variable level of current by the variable current source to the capacitor bank.

8 . The method of claim 7 , further comprising programming the capacitor bank to activate a specific number of capacitors using most significant bits (MSB) of a digital to analog conversion (DAC) code that represents a target voltage at an output terminal of the inductor.

9 . The method of claim 7 , wherein the controller comprises a sample and hold circuit having a set point that is substantially equal to a voltage at an output terminal of the inductor.

10 . The method of claim 9 , wherein the sample and hold circuit is coupled to a comparator.

11 . The method of claim 10 , further comprising sampling an output voltage of the capacitor bank, by the sample and hold circuit, and transmitting the sampled output voltage of the capacitor bank to the comparator and comparing the sampled output voltage to the voltage at the output terminal of the inductor, by the comparator.

12 . The method of claim 11 , further comprising stopping supplying current to the inductor when the output voltage of the capacitor bank is equal to the voltage at the output terminal of the inductor.

Assignees

• Empower Semiconductor Inc

Inventors

• Lidsky David
• Phillips Timothy Alan
• Oak Parag

Classifications

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/01

  Resonant DC/DC converters · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title