Method for manufacturing trench-gate MOSFET

Patent metadata

Field	Value
Publication number	US-12469706-B2
Application number	US-202217951543-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	Sep 24, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

The present disclosure relates to a method for manufacturing a trench-gate MOSFET. In the method, a first trench is formed in a first region and a second trench is formed in a second region in an epitaxial layer. A first well is formed in a bottom surface of the first trench in the first region, and a body region is formed in the epitaxial layer in the second region, simultaneously in one ion implantation process with one mask being used. Thus, the method reduces a number of masks and simplifies ion implantation processes, thereby reducing manufacturing cost.

First claim

What is claimed is:

1. A method for manufacturing a trench-gate MOSFET, comprising:
forming an epitaxial layer of a first dopant type on a first surface of a substrate of a first dopant type;
etching the epitaxial layer to form a first trench in a first region and a second trench in a second region;
implanting ions into a bottom surface of the first trench in the first region to form a first well, and into a surface of the epitaxial layer in the second region to form a second well as a body region, the first well and the second well being of a second dopant type opposite to the first dopant type;
forming a first insulating layer on a surface of the epitaxial layer and in the first trench and the second trench, the first insulating layer surrounding sidewall of the first trench and the second trench to form cavities in the first trench and the second trench;
forming a polysilicon layer which fills the cavities, and etching back the polysilicon layer to remove a portion of the polysilicon layer in the second trench;
etching back the first insulating layer to expose an upper portion of the second trench;
forming a gate dielectric on an inner wall of the upper portion of the second trench, the gate dielectric covering a remaining portion of the polysilicon layer in the second trench;
forming a gate conductor in the upper portion of the second trench; and
forming a source region of the first dopant type in the body region,
wherein the step of implanting ions into the bottom surface of the first trench in the first region to form the first well, and into the surface of the epitaxial layer in the second region to form the second well comprises:
providing a patterned mask which shields the surface of the epitaxial layer in the first region and the second trench in the second region; and
implanting ions on a first surface of the epitaxial layer through the patterned mask, wherein the first well is formed by the ions implanted in the bottom surface of the first trench; and
the second well is formed by the ions implanted in the surface of the epitaxial layer.

2. The method according to claim 1 , between the steps of etching back the polysilicon layer and etching back the first insulating layer, further comprising:
forming a second insulating layer on the first insulating layer, the second insulating layer filling the cavity in the second trench.

3. The method according to claim 1 , after the step of forming a source region of the first dopant type in the body region, further comprising:
forming an interlayer dielectric on a first surface of the epitaxial layer;
forming through holes which penetrate the interlayer dielectric, and which expose the polysilicon layer in the first region and the gate conductor and the source region in the second region, respectively;
forming a contact region of the second dopant type in the source region via one of the through holes; and
forming conductive vias which contact the polysilicon layer in the first region and the gate conductor and the source region in the second region, respectively.

4. The method according to claim 1 , wherein the first dopant type is of an N type and the second dopant type is of a P type.

Assignees

• Hangzhou Silicon Magic Semiconductor Tech Co Ltd
• Silicon Magic Semiconductor Tech Hangzhou Co Ltd

Inventors

• Sun He

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title