Memory device and wrap around read method thereof

Patent metadata

Field	Value
Publication number	US-12469528-B2
Application number	US-202418410985-A
Country	US
Kind code	B2
Filing date	Jan 11, 2024
Priority date	Feb 4, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A memory device including a memory cell array, a signal generator, a word line decoder, a bit line decoder, a sensing amplifier circuit and a register circuit is provided. The signal generator generates a control signal according to a wrap around read command. The word line decoder, the bit line decoder, and the sensing amplifier circuit read data stored in the memory cell array according to the wrap around read command, so as to output a first wrap around read data. The register circuit is configured to latch the first wrap around read data and outputs successive wrap around read data according to the control signal and the latched first wrap around read data after the first wrap around read data is output. When the register circuit outputs the successive wrap around read data, the word line decoder, the bit line decoder, and the sensing amplifier circuit are disable.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory cell array, configured to store data; a signal generator, configured to generate a control signal according to a wrap around read command; a word line decoder, coupled to the memory cell array and configured to receive the control signal; a bit line decoder, coupled to the memory cell array and configured to receive the control signal; a sensing amplifier circuit, coupled to the bit line decoder and configured to receive the control signal; and a register circuit, coupled to the sensing amplifier circuit and configured to receive the control signal; wherein, the word line decoder, the bit line decoder, and the sensing amplifier circuit are configured to perform a first read to the data stored in the memory cell array according to the wrap around read command to output first wrap around read data, wherein, the register circuit is configured to latch the first wrap around read data, and output successive wrap around read data according to the control signal and the first wrap around read data that is latched after the first wrap around read data is output, wherein, during a period when the register circuit outputs the successive wrap around read data, the word line decoder, the bit line decoder, and the sensing amplifier circuit are disabled according to the control signal.

2 . The memory device according to claim 1 , wherein the signal generator generates and outputs the control signal according to a clock signal, the wrap around read command, and a register circuit initial state setting signal.

3 . The memory device according to claim 2 , wherein the register circuit initial state setting signal is configured to set an initial state of the register circuit after power-on.

4 . The memory device according to claim 2 ,
wherein, the signal generator generates the control signal of a second level during the first read, so that the sensing amplifier circuit provides the first wrap around read data to the register circuit and an output terminal, wherein, the signal generator generates the control signal of a first level during the period when the register circuit outputs the successive wrap around read data, so that the word line decoder, the bit line decoder, and the sensing amplifier circuit are disabled according to the control signal at the first level.

5 . The memory device according to claim 4 , wherein the signal generator comprises:
a first switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to a first voltage, and the control terminal of the first switch is coupled to a first clock; a second switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch, the second terminal of the second switch is coupled to a second voltage, and the control terminal of the second switch is coupled to a second clock; a first latch circuit, having a first terminal and a second terminal, wherein the first terminal of the first latch circuit is coupled to the second terminal of the first switch and the first terminal of the second switch; a third switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first latch circuit, and the control terminal of the third switch is coupled to an inverted signal of the first clock; a fourth switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch, the second terminal of the fourth switch is coupled to the second voltage, and the control terminal of the fourth switch is coupled to the register circuit initial state setting signal; and a second latch circuit, having a first terminal and a second terminal, wherein the first terminal of the second latch circuit is coupled to the second terminal of the third switch and the first terminal of the fourth switch, and the second terminal of the second latch circuit serves as an output terminal of the signal generator, wherein the control signal is output from the output terminal of the signal generator.

6 . The memory device according to claim 5 , wherein the first switch and the third switch are not turned on at a same time.

7 . The memory device according to claim 5 , wherein the first clock turns off the first switch, the inverted signal of the first clock turns on the third switch, and the second clock turns on the second switch, so that the second voltage is transmitted to the output terminal of the signal generator through the second switch, the first latch circuit, the third switch, and the second latch circuit to generate the control signal of the second level.

8 . The memory device according to claim 5 , wherein during the period when the register circuit outputs the successive wrap around read data, the first clock turns on the first switch, and the inverted signal of the first clock turns off the third switch, so that after the first voltage passes through the first switch, the first voltage is latched in the first latch circuit, next, the first clock turns off the first switch, and the inverted signal of the first clock turns on the third switch, so that the first voltage passes through the third switch and the second latch circuit and is transmitted to the output terminal of the signal generator to generate the control signal of the first level.

9 . The memory device according to claim 8 , wherein the second clock turns off the second switch, and the register circuit initial state setting signal turns off the fourth switch during the period when the register circuit outputs the successive wrap around read data.

10 . The memory device according to claim 1 , wherein the register circuit comprises:
a first transistor, a second transistor, a third transistor, and a fourth transistor, sequentially connected in series between a first voltage and a second voltage; and a first inverter and a second inverter, forming a latch, coupled to the second transistor and the third transistor, wherein the latch is configured to latch sensing data output by the sensing amplifier circuit.

11 . The memory device according to claim 10 , wherein the first transistor is controlled by the control signal, the second transistor and the third transistor are jointly controlled by the sensing data output by the sensing amplifier circuit, and the fourth transistor is controlled by an inverted signal of the control signal.

12 . The memory device according to claim 1 , wherein the register circuit comprises a register, a switch circuit, and an output terminal, and the sensing amplifier circuit is coupled to the register and the output terminal through the switch circuit.

13 . The memory device according to claim 1 , wherein the control signal having a first level controls a switch circuit so that the sensing amplifier circuit is not connected to the register circuit and an output terminal; and the control signal having a second level controls the switch circuit so that the sensing amplifier circuit is connected to the register circuit and the output terminal.

14 . A wrap around read method of a memory device, wherein the memory device comprises a memory cell array, a word line decoder, a bit line decoder, a sensing amplifier circuit, and a register circuit, the wrap around read method comprises:
performing a first read to data stored in the memory cell array by using the word line

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Chen Chung-Zen

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title