Display device and display driving method

Patent metadata

Field	Value
Publication number	US-12469464-B2
Application number	US-202418733342-A
Country	US
Kind code	B2
Filing date	Jun 4, 2024
Priority date	Sep 16, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Embodiments of the present disclosure relate to a display device, comprising: a display panel including a light emitting element, a driving transistor configured to provide a driving current to the light emitting element, and a plurality of switching transistors configured to control an operation of the driving transistor; a gate driving circuit configured to supply a plurality of scan signals to the display panel; a data driving circuit configured to supply a plurality of data voltages to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, wherein a bias voltage is supplied to the driving transistor in a first period in which the data voltage is supplied to the display panel at a low speed mode which the display panel is driven at a low speed driving frequency.

First claim

What is claimed is:

1 . A display device, comprising:
a display panel including a light emitting element, a driving transistor having a first node being a gate electrode, a second node being a drain electrode, and a third node being a source electrode, and configured to provide a driving current to the light emitting element, a plurality of switching transistors configured to control an operation of the driving transistor, and a storage capacitor having first electrode and second electrode; a gate driving circuit configured to supply a plurality of scan signals to the display panel; wherein the plurality of switching transistors include; a first switching transistor turned on by a first scan signal, the first switching transistor configured to diode-connect the first node and the third node; a second switching transistor turned on by a second scan signal, the second switching transistor configured to supply a data voltage or a bias voltage to the second node; a third switching transistor turned on by a light emitting signal, the third switching transistor configured to supply a high potential driving voltage from a fourth node connected to the first electrode of the storage capacitor to the second node; a fourth switching transistor turned on by the light emitting signal, the fourth switching transistor configured to form a current path between the driving transistor and the light emitting element; and a fifth switching transistor turned on by a third scan signal, the fifth switching transistor configured to supply a first voltage to the first node, wherein the first electrode of the storage capacitor is connected to the fourth node, wherein the second electrode of the storage capacitor is connected to the first node, wherein the display panel including a plurality of subpixels, driven in a high-speed mode at a high driving frequency and in a low-speed mode at a low driving frequency that is less than the high driving frequency, wherein a data voltage is supplied to the display panel during a first period and the bias voltage is supplied to the driving transistor in a second period in the low-speed mode, and wherein the second period is a period after the first period and before a light emitting period of the light emitting element.

2 . The display device of claim 1 , wherein the plurality of switching transistors further comprise a sixth switching transistor turned on by fourth scan signal, the sixth switching transistor configured to apply a second voltage to a fifth node, wherein the fifth node is an anode electrode of the light emitting element.

3 . The display device of claim 2 , wherein the fourth scan signal is based on the second scan signal.

4 . The display device according to claim 2 , further comprising,
a data driving circuit configured to supply a plurality of data voltages to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, wherein the bias voltage is supplied to the driving transistor in the second period in which the data voltage from the plurality of data voltages is supplied to the display panel at the low-speed mode which the display panel is driven under a predetermined speed frequency, wherein the bias voltage is supplied after the first period for a characteristic value of the driving transistor and before the light emitting period of the light emitting element in the second period, wherein the plurality of data voltages are supplied to the display panel during the first period.

5 . The display device according to claim 4 , wherein a level of the first voltage or the second voltage is controlled in a third period in which the data voltage is not supplied to the display panel after the second period in the low-speed mode.

6 . The display device according to claim 5 , wherein the first voltage is determined according to a level or grayscale of the data voltage supplied to the display panel in the second period.

7 . The display device according to claim 5 , wherein the second voltage is determined according to a level of a low potential driving voltage supplied to a cathode electrode of the light emitting element in the second period.

8 . The display device according to claim 5 , wherein the bias voltage is supplied to the driving transistor in the third period in which the data voltage is not supplied to the display panel after the second period at the low-speed mode.

9 . The display device according to claim 8 , wherein the bias voltage is supplied to the driving transistor more than one time in the third period.

10 . The display device according to claim 8 , wherein the bias voltage supplied in the second period and the bias voltage supplied to the third period have different voltage levels.

11 . The display device according to claim 8 , wherein the bias voltage is controlled at a time when the display panel is driven from the high-speed mode, which is driven at a frequency higher than the predetermined speed frequency, to the low-speed mode.

12 . The display device according to claim 5 , wherein the first voltage is controlled at a time when the display panel is driven from the high-speed mode, which is driven at a frequency higher than the predetermined speed frequency, to the low-speed mode.

13 . The display device according to claim 5 , wherein the second voltage is controlled at a time when the display panel is driven from the high-speed mode, which is driven at a frequency higher than the predetermined speed frequency, to the low-speed mode.

14 . The display device of claim 1 , wherein the third scan signal is based on the first scan signal.

15 . The display device of claim 14 , wherein the third scan signal includes the first scan signal that is provided to a first subpixel which is located on a different location of a second subpixel comprising the driving transistor and the plurality of switching transistors.

16 . The display device of claim 14 , wherein the third scan signal is used as the first scan signal at another gate line which is different from a gate line connected with the second switching transistor according to a driving phase of the display panel.

17 . The display device of claim 1 , wherein the first switching transistor is an oxide transistor.

18 . The display device of claim 1 , wherein the fifth switching transistor is an oxide transistor.

19 . The display device according to claim 1 , wherein the plurality of switching transistors further comprise:
a seventh switching transistor turned on by a fifth scan signal, the seventh switching transistor configured to supply the bias voltage to the third node.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Jaemin
• Park Subin
• Kim Bonghwan
• Song Won-Seok

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title