Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12469457-B2
Application number	US-202418955129-A
Country	US
Kind code	B2
Filing date	Nov 21, 2024
Priority date	May 6, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a light-emitting element in response to a first reset control voltage to reversely bias the light-emitting element.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; and a plurality of sub-pixels, located on the base substrate and arranged in an array, wherein each of the plurality of sub-pixels comprises a pixel circuit, and the pixel circuit is configured to drive a light-emitting element corresponding to the each of the plurality of sub-pixels to emit light; each of the plurality of pixel circuits comprises a drive sub-circuit, a first reset sub-circuit and a second reset sub-circuit; the drive sub-circuit comprises a control terminal, a first terminal, and a second terminal, and the drive sub-circuit is configured to be connected with the light-emitting element and control a drive current flowing through the light-emitting element; the first reset sub-circuit comprises a first reset transistor, a gate electrode of the first reset transistor is configured to receive a first reset control voltage, a first electrode of the first reset transistor is configured to receive a first reset voltage, and a second electrode of the first reset transistor is configured to be connected with the light-emitting element; the first reset transistor is configured to apply the first reset voltage to the light-emitting element to reversely bias the light-emitting element in response to the first reset control voltage; the second reset sub-circuit is connected with the control terminal of the drive sub-circuit and is configured to apply a second reset voltage to the control terminal of the drive sub-circuit in response to a second reset control voltage, to reset the control terminal of the drive sub-circuit; the plurality of sub-pixels are arranged in a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, and comprise a first sub-pixel and a second sub-pixel in a same pixel row; the display substrate further comprises a first reset voltage line and a second reset voltage line which are both extended along the first direction; the first reset voltage line is electrically connected with the first electrode of the first reset transistor of the first sub-pixel, and the second reset voltage line is electrically connected with the first electrode of the first reset transistor of the second sub-pixel; the display substrate further comprises a first reset voltage terminal, and the first reset voltage terminal is electrically connected with the first reset voltage line to provide the first reset voltage to the first reset transistor of the first sub-pixel.

2 . The display substrate according to claim 1 , further comprising a second reset voltage terminal,
wherein the second reset voltage terminal is electrically connected with the second reset sub-circuit to provide the second reset voltage, and the second reset voltage output by the second reset voltage terminal is greater than the first reset voltage output by the first reset voltage terminal.

3 . The display substrate according to claim 1 , further comprising a second reset voltage terminal,
wherein the second reset voltage terminal is electrically connected with the second reset voltage line to provide the first reset voltage to the first reset transistor of the second sub-pixel.

4 . The display substrate according to claim 3 , wherein the first reset voltage output by the first reset voltage terminal is different from the first reset voltage output by the second reset voltage terminal.

5 . The display substrate according to claim 3 , wherein the first reset voltage output by the first reset voltage terminal is same as the first reset voltage output by the second reset voltage terminal.

6 . The display substrate according to claim 3 , wherein the plurality of sub-pixels further comprise a third sub-pixel;
the first sub-pixel, the second sub-pixel, and the third sub-pixel are in the same pixel row; the first reset voltage line electrically connects the first electrode of the first reset transistor of the first sub-pixel with the first reset voltage terminal, and the second reset voltage line electrically connects both the first electrode of the first reset transistor of the second sub-pixel and the first electrode of the first reset transistor of the third sub-pixel with the second reset voltage terminal.

7 . The display substrate according to claim 1 , wherein each of the plurality of pixel circuits further comprises a compensation sub-circuit;
the compensation sub-circuit comprises a control terminal, a first terminal and a second terminal, and the control terminal of the compensation sub-circuit is configured to receive a second scanning signal, the first terminal and the second terminal of the compensation sub-circuit are respectively electrically connected with the control terminal and the second terminal of the drive sub-circuit, and the compensation sub-circuit is configured to compensate a threshold value of the drive sub-circuit in response to the second scanning signal.

8 . The display substrate according to claim 7 , wherein the second reset sub-circuit comprises a second reset transistor, and the compensation sub-circuit comprises a compensation transistor; and
the second reset transistor and the compensation transistor are both dual-gate transistors.

9 . The display substrate according to claim 7 , further comprising a first reset signal line extended along the first direction, wherein the first reset signal line is connected with the second reset sub-circuit to provide the second reset voltage, and
the first reset signal line is at a side of the first reset voltage line close to the base substrate.

10 . The display substrate according to claim 9 , wherein the first reset signal line comprises a doped semiconductor material.

11 . The display substrate according to claim 9 , further comprising a second reset signal line,
wherein the second reset signal line is at a side of the first reset voltage line away from the base substrate and is electrically connected with the first reset signal line.

12 . The display substrate according to claim 11 , wherein each of the plurality of pixel circuits further comprises a storage sub-circuit;
the storage sub-circuit comprises a storage capacitor, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode; and the second capacitor electrode is at a side of the first capacitor electrode close to the base substrate.

13 . The display substrate according to claim 12 , further comprising a plurality of first power lines and a plurality of second power lines extended along the second direction,
wherein each of the plurality of first power lines is electrically connected with first capacitor electrodes of sub-pixels to provide a first power supply voltage; the plurality of second power lines and the plurality of first power lines are arranged in one-to-one correspondence, and each of the plurality of second power lines and a corresponding first power line are electrically connected through a via hole.

14 . The display substrate according to claim 12 , wherein each of the plurality of pixel circuits further comprises a connection electrode;
the connection electrode and the second reset signal line are in a same layer and insulated from each other, and the connection electrode is respectively electrically connected with the second capacitor electrode and the first terminal of the compensation sub-circuit.

15 . The display substrate according to claim 12 , wherein the first capacitor electrode comprises an opening, and the second connection electrode is insulated from the first capacitor electrod

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Lu Hongting
• Feng Yuhsiung
• Mou Xin
• Chen Chenyu
• Zhao Shuang
• Yang Zhongliu
• Yang Jing
• Chen Wenbo

Classifications

• G09G2330/026

  Arrangements or methods related to booting a display · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0272

  Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title