Pixel circuit and driving method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-12469446-B2
Application number	US-202218257940-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A pixel circuit includes a driving sub-circuit coupled to a first node, a second node and a third node, a compensation sub-circuit coupled to the first node, the third node and a first scan signal terminal, an adjustment sub-circuit, and a writing sub-circuit. The compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series. A fourth node is formed between a second electrode of a first first transistor and a first electrode of a second first transistor. The adjustment sub-circuit is coupled to the fourth node and at least one control terminal. The adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node.

First claim

What is claimed is:

1 . A display panel, comprising:
a plurality of pixel circuits; and light-emitting devices electrically connected to the pixel circuits; wherein each pixel circuit of the plurality of pixel circuits comprises a driving sub-circuit, a compensation sub-circuit, an adjustment sub-circuit and a writing sub-circuit, wherein
the driving sub-circuit is coupled to a first node, a second node and a third node; the driving sub-circuit is configured to, in a writing phase, transmit a voltage from the second node to the third node under a control of a voltage of the first node;
the writing sub-circuit is coupled to the second node, a second scan signal terminal and a data signal terminal; the writing sub-circuit is configured to: in the writing phase, transmit a data signal received at the data signal terminal to the second node under a control of a gate scan signal received from the second scan signal terminal; and in an adjustment phase, transmit the data signal received at the data signal terminal to the second node under the control of the gate scan signal received from the second scan signal terminal, so as to reset the second node;
the compensation sub-circuit is coupled to the first node, the third node and a first scan signal terminal; the compensation sub-circuit is configured to: in an initialization phase, transmit the voltage of the first node to the third node under a control of a scan signal transmitted from the first scan signal terminal; and in the writing phase, transmit a voltage of the third node to the first node under the control of the scan signal transmitted from the first scan signal terminal; wherein
the compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series; and
gates of all the first transistors in the first transistor group are coupled to the first scan signal terminal, a first electrode of a first first transistor in the first transistor group is coupled to the first node, and a second electrode of a last first transistor in the first transistor group is coupled to the third node; a fourth node is formed between a second electrode of the first first transistor in the first transistor group and a first electrode of a second first transistor in the first transistor group; and

the adjustment sub-circuit is coupled to the fourth node and at least one control terminal; the adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node; wherein the display panel further comprises:
a substrate and a first gate conductive layer located on a side of the substrate, wherein
the first gate conductive layer includes an enable signal line extending in a first direction; the adjustment sub-circuit includes a second transistor, and the enable signal line includes at least a third portion; the third portion is further used as a gate of the second transistor; and

a second gate conductive layer located on a side of the first gate conductive layer away from the substrate and a first source-drain conductive layer located on a side of the second gate conductive layer away from the substrate, wherein
the first source-drain conductive layer includes reference voltage lines extending in a second direction; the second direction and the first direction intersect;
an orthographic projection of a reference voltage line on the substrate is at least partially overlapped with an orthographic projection of the gate of the second transistor on the substrate; and
an overlapping area of the orthographic projection of the reference voltage line on the substrate and an orthographic projection of the fourth node on the substrate is less than 50% of an area of the orthographic projection of the fourth node on the substrate; or

wherein the display panel further comprises:
the substrate and the first gate conductive layer located on the side of the substrate, wherein
the first gate conductive layer includes the enable signal line extending in the first direction; the adjustment sub-circuit includes the second transistor; the pixel circuit further includes a fourth transistor and a fifth transistor; a gate of the fourth transistor is coupled to an enable signal terminal, a first electrode of the fourth transistor is coupled to a first voltage terminal, and a second electrode of the fourth transistor is coupled to the second node; a gate of the fifth transistor is coupled to the enable signal terminal, a first electrode of the fifth transistor is coupled to the third node, and a second electrode of the fifth transistor is coupled to a light-emitting device; and
the enable signal line includes the third portion, a fourth portion and a fifth portion; the third portion is further used as the gate of the second transistor, the fourth portion is further used as the gate of the fourth transistor, and the fifth portion is further used as the gate of the fifth transistor; wherein the gate of the second transistor is located on a side of the gate of the fifth transistor away from the gate of the fourth transistor; and

the second gate conductive layer located on the side of the first gate conductive layer away from the substrate and the first source-drain conductive layer located on the side of the second gate conductive layer away from the substrate, wherein
the first source-drain conductive layer includes the reference voltage lines extending in the second direction; the second direction and the first direction intersect;
the orthographic projection of the reference voltage line on the substrate is at least partially overlapped with the orthographic projection of the gate of the second transistor on the substrate;
the overlapping area of the orthographic projection of the reference voltage line on the substrate and the orthographic projection of the fourth node on the substrate is less than 50% of the area of the orthographic projection of the fourth node on the substrate.

2 . The display panel according to claim 1 , wherein
the pixel circuit further includes the fifth transistor; the gate of the fifth transistor is coupled to the enable signal terminal, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the light-emitting device; the reference voltage line includes a first body portion and a second body portion each extending in the second direction; the reference voltage line further includes a first connection portion connected between the first body portion and the second body portion and extending in the first direction; an orthographic projection of an end of the first connection portion on the substrate is overlapped with the orthographic projection of the gate of the second transistor on the substrate, and an orthographic projection of another end of the first connection portion on the substrate is overlapped with an orthographic projection of the gate of the fifth transistor on the substrate.

3 . The display panel according to claim 1 , wherein
the first source-drain conductive layer further includes a first connection line; the first electrode of the second transistor is coupled to the reference voltage line; the second electrode of the second transistor is coupled to the fourth node through the first connection line; the reference voltage line is bent in the first direction, so that the orthographic projection of the reference voltage line on the substrate is non-overlapped with an orthographic projection of the first connection line on the substrate.

4 . The display panel according to claim 1 , wherein
the driving sub-circuit includes a

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhang Jingwen
• Wang Miao
• Zhang Tiaomei
• Xiao Yunsheng
• Qing Haigang

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title