Expandable neuromorphic circuit

Patent metadata

Field	Value
Publication number	US-12468927-B2
Application number	US-202117205620-A
Country	US
Kind code	B2
Filing date	Mar 18, 2021
Priority date	Oct 29, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

First claim

What is claimed is:

1 . A neuromorphic circuit comprising:
a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal; wherein the first connecting block connects column lines in the first synapse array respectively to an equal number of column lines in the second synapse array, wherein the first connecting block includes a plurality of switches for transmitting signals of input lines or output lines of the first synapse circuits in response to the control signal, each of the plurality of switches connecting a column line in the first synapse array to a column line in the second synapse array, and wherein each of the plurality of switches includes complementary pass transistor logic (CPTL) that transmits a same signal level as a signal level in the column line in the first synapse array to the column line in the second synapse array.

2 . The neuromorphic circuit of claim 1 , further comprising:
a second neuron array positioned between the first synapse array and the first connecting block; and a third neuron array connected to the output lines of the second synapse array and generating an output spike signal.

3 . The neuromorphic circuit of claim 1 , further comprising:
a third synapse array formed in a second direction perpendicular to the first synapse array; and a second connecting block connecting the first synapse array and the third synapse array, wherein the second synapse array is formed in a first direction with respect to the first synapse array.

4 . The neuromorphic circuit of claim 3 , further comprising:
a second neuron array formed between the first synapse array and the second connecting block.

5 . A neuromorphic circuit comprising:
a first neuron array arranged in a column direction and including a plurality of first neuron circuits generating first spike signals; a first synapse array including a plurality of first synapse circuits processing and outputting the first spike signals transmitted from the first neuron array; a second synapse array positioned in a row direction of the first synapse array and including a plurality of second synapse circuits receiving the first spike signals; a second neuron array arranged in the column direction and including a plurality of second neuron circuits generating second spike signals; a third synapse array including a plurality of third synapse circuits processing and outputting the second spike signals transmitted from the second neuron array; a fourth synapse array positioned in the row direction of the third synapse array and including a plurality of fourth synapse circuits receiving the second spike signals; a first connecting block positioned between the first synapse array and the third synapse array and connecting the first synapse array and the third synapse array in response to a control signal; a second connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to the control signal; a third connecting block positioned between the second synapse array and the fourth synapse array and connecting the second synapse array and the fourth synapse array in response to the control signal; a fourth connecting block positioned between the third synapse array and the fourth synapse array and connecting the third synapse array and the fourth synapse array in response to the control signal; and a control logic to generate the control signal; wherein the first connecting block connects column lines in the first synapse array respectively to an equal number of column lines in the third synapse array, wherein each of the first to fourth connecting blocks includes complementary pass transistor logic configured to transmit a same signal level as a signal level in a column line in a transmitting synapse array to a column line in a receiving synapse array, wherein the first connecting block and the third connecting block extend in the row direction and the second connecting block and the fourth connecting block extend in the column direction, wherein the first connecting block extends across all of the column lines in the first synapse array and all of the column lines in the third synapse array, and the third connecting block extends across all of the column lines in the second synapse array and all of the column lines in the fourth synapse array, and wherein in a plan view the first connecting block, the second connecting block, the third connecting block and the fourth connecting block form a cruciform shape.

6 . The neuromorphic circuit of claim 5 , further comprising:
a third neuron array connected to output lines of the third synapse array and generating a first output spike signal; and a fourth neuron array connected to the output lines of the fourth synapse array and generating a second output spike signal.

7 . The neuromorphic circuit of claim 5 , wherein the first connecting block comprises a plurality of first switches each including a CPTL device for transmitting output signals of the first synapse circuits to the third synapse circuit without level change in response to the control signal.

8 . The neuromorphic circuit of claim 7 , wherein the second connecting block comprises a plurality of second switches each including a CPTL device for transmitting the first spike signals transmitted from the first neuron array to the second synapse circuit without changing a level in response to the control signal.

9 . The neuromorphic circuit of claim 8 , wherein the third connecting block comprises a plurality of third switches each including a CPTL device for transmitting output signals of the second synapse circuits to the fourth synapse circuit without changing a signal level in response to the control signal.

10 . The neuromorphic circuit of claim 9 , wherein the fourth connecting block comprises a plurality of fourth switches each including a CPTL device for transmitting the second spike signals transmitted from the second neuron array to the fourth synapse circuit without changing a level in response to the control signal.

11 . The neuromorphic circuit of claim 5 , further comprising:
a third neuron array positioned between the first synapse array and the first connecting block; and a fourth neuron array positioned between the second synapse array and the third connecting block.

12 . The neuromorphic circuit of claim 11 , further comprising:
a fifth neuron array connected to output lines of the third synapse array and generating first output spike signals; and a sixth neuron array connected to the output lines of the fourth synapse array and generating second output spike signals.

13 . A neuromorphic circuit comprising:
a first synapse array including a plurality of first synapse circuits for processing and outputting input spike signals; a second synapse array including a plurality of second synapse circuits; and a connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; wherein the connecting

Assignees

• Korea Inst Sci & Tech

Inventors

• Kwak Joon Young
• Lee Suyoun
• Kim Inho
• Park Jong-Keuk
• Lee Kyeong Seok
• Kim Jaewook
• Park Jongkil
• Jeong Yeonjoo
• Hwang Gyuweon

Classifications

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G11C11/54 Primary

  using elements simulating biological cells, e.g. neuron · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title