System and method for signaling interface status using a single indicator

Patent metadata

Field	Value
Publication number	US-12468615-B2
Application number	US-202418420516-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Jan 23, 2024
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A flash definition specifying a flashing sequence for a status indicator of a multi-lane port is stored on a device. In operation, the status indicator is lit, following the flashing sequence, to indicate a current lane state (in a Port/Lane Signaling Mode) or interface/channel state (in an Interface/Channel Signaling Mode). The flashing sequence may begin with a preamble, indicating a start of the flashing sequence. The device may have different multi-lane ports, each having one or more status indicators configured for indicating states of multiple lanes or a state of an interface having a multiple of component lanes. Flashing sequences for these ports are synchronizable (to the port having the largest number of lanes or, in the Interface/Channel Signaling Mode, the largest number of configured interfaces on that port). The lanes of a multi-lane port may operate at the same or different speeds and may be bundled into interfaces/channels.

First claim

What is claimed is:

1 . A status signaling method, the method comprising:
determining a flash definition that specifies a flashing sequence for a status indicator of a multi-lane port, the multi-lane port having a plurality of component lanes; storing the flash definition on a device with the multi-lane port; and configuring the multi-lane port utilizing the flash definition such that, in operation, the status indicator is lit, following the flashing sequence specified in the flash definition, to indicate a current state of a respective component lane of the plurality of component lanes or of a subset of the plurality of component lanes of the multi-lane port, wherein the subset of the plurality of component lanes corresponds to an interface or channel.

2 . The status signaling method according to claim 1 , wherein the flash definition comprises a preamble, status colors each corresponding to a lane state or to an interface state, a flash duration, a pause, and a pause duration.

3 . The status signaling method according to claim 1 , wherein the flashing sequence begins with a preamble and wherein the preamble indicates a start of the flashing sequence.

4 . The status signaling method according to claim 1 , wherein the device comprises a networking device having multi-lane ports, wherein the multi-lane ports are configured with flashing sequences having a first sequence length and a second sequence length, and wherein the second sequence length is longer than the first sequence length.

5 . The status signaling method according to claim 4 , further comprising:
synchronizing the flashing sequences for the multi-lane ports to one of the flashing sequences having the second sequence length.

6 . The status signaling method according to claim 1 , wherein the plurality of component lanes operates at same speed or different speeds.

7 . The status signaling method according to claim 1 , wherein the status indicator is one of a plurality of status indicators for the multi-lane port, wherein each of the plurality of status indicators is configured for indicating a state of one or more component lanes or one or more interfaces, and wherein an interface includes one or more component lanes.

8 . A system, comprising:
a status indicator for a multi-lane port on a device, the multi-lane port having a plurality of component lanes; a processor; a non-transitory computer-readable medium; and a flash definition and instructions stored on the non-transitory computer-readable medium, the flash definition specifying a flashing sequence for the status indicator, the instructions translatable by the processor for controlling, based at least on the flash definition, the status indicator such that, in operation, the status indicator is lit, following the flashing sequence specified in the flash definition, to indicate a current state of a respective component lane of the plurality of component lanes or a subset of the plurality of component lanes of the multi-lane port, wherein the subset of the plurality of component lanes corresponds to an interface or channel.

9 . The system of claim 8 , wherein the flash definition comprises a preamble, status colors each corresponding to a lane state or to an interface state, a flash duration, a pause, and a pause duration.

10 . The system of claim 8 , wherein the flashing sequence begins with a preamble and wherein the preamble indicates a start of the flashing sequence.

11 . The system of claim 8 , wherein the device comprises a networking device having multi-lane ports, wherein the multi-lane ports are configured with flashing sequences having a first sequence length and a second sequence length, and wherein the second sequence length is longer than the first sequence length.

12 . The system of claim 11 , wherein the instructions are further translatable by the processor for synchronizing the flashing sequences for the multi-lane ports to one of the flashing sequences having the second sequence length.

13 . The system of claim 8 , wherein the plurality of component lanes operates at same speed or different speeds.

14 . The system of claim 8 , wherein the status indicator is one of a plurality of status indicators for the multi-lane port, wherein each of the plurality of status indicators is configured for indicating a state of one or more component lanes or one or more interfaces, wherein an interface includes one or more component lanes.

15 . An apparatus, comprising:
a multi-lane port having a plurality of component lanes; a status indicator for the multi-lane port; a non-transitory computer-readable medium storing a flash definition that specifies a flashing sequence for the status indicator; and a processor configured for controlling, based at least on the flash definition, the status indicator such that, in operation, the status indicator is lit, following the flashing sequence specified in the flash definition, to indicate a current state of a respective component lane of the plurality of component lanes or a subset of the plurality of component lanes of the multi-lane port, wherein the subset of the plurality of component lanes corresponds to an interface or channel.

16 . The apparatus of claim 15 , wherein the flash definition comprises a preamble, status colors each corresponding to a lane state or to an interface state, a flash duration, a pause, and a pause duration.

17 . The apparatus of claim 15 , further comprising:
a plurality of multi-lane ports configured with flashing sequences, the flashing sequences having a first sequence length and a second sequence length, wherein the second sequence length is longer than the first sequence length.

18 . The apparatus of claim 17 , wherein the processor is further configured for synchronizing the flashing sequences for the plurality of multi-lane ports to one of the flashing sequences having the second sequence length.

19 . The apparatus of claim 15 , wherein the plurality of component lanes operates at same speed or different speeds.

20 . The apparatus of claim 15 , wherein the status indicator is one of a plurality of status indicators for the multi-lane port, wherein each of the plurality of status indicators is configured for indicating a state of one or more component lanes or one or more interfaces, and wherein an interface includes one or more component lanes.

Assignees

• Arista Networks Inc

Inventors

• Peach John
• Wang Harold
• Hull Martin

Classifications

• G08B5/38

  using flashing light · CPC title

• G06F11/325 Primary

  by lamps or LED's · CPC title

• H04Q1/136 Primary

  having patch field management or physical layer management arrangements · CPC title