Boot initialization without home node involvement

Patent metadata

Field	Value
Publication number	US-12468543-B2
Application number	US-202318133971-A
Country	US
Kind code	B2
Filing date	Apr 12, 2023
Priority date	Jan 6, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.

First claim

What is claimed is:

1 . A system comprising:
a first node coupled to a memory region storing data associated with a boot process, wherein the first node comprises a boot handler and a first node identifier; a second node comprising a second node identifier associated with one or more nodes storing physical locations associated with a memory address; and a functional unit comprising a processor and address management circuitry, the address management circuitry configured to:
receive a request from the processor, wherein the request comprises the memory address associated with the second node identifier and is associated with the boot process initialized at the processor;
determine that a bit stored at the address management circuitry has a first value indicating to associate the request with the first node identifier bypassing the second node; and
transmit the request with the first node identifier to the boot handler at the first node in response to determining the bit has the first value.

2 . The system of claim 1 , wherein the processor is configured to:
receive the data associated with the boot process from the memory region; and program a node identification table of the address management circuitry in response to receiving the data.

3 . The system of claim 1 , wherein the processor is configured to:
receive the data associated with the boot process from the memory region; erase one or more caches in the system in response to receiving the data; and program the bit to a second value indicating to associate incoming memory addresses with the second node identifier in response to erasing the one or more caches.

4 . The system of claim 1 , wherein the processor is configured to:
receive the data associated with the boot process from the memory region; and program the bit stored at the address management circuitry to a second value indicating to associate an incoming memory address with the second node identifier.

5 . The system of claim 1 , wherein the boot handler coupled to the memory region is configured to:
receive one or more operation codes corresponding to one or more operations in response to the processor receiving the data associated with the boot process; select a second operation code in response to receiving the one or more operation codes; and transmit the second operation code to a logic component associated with the memory region.

6 . The system of claim 1 , wherein the address management circuitry is further configured to:
receive a second request from the processor; determine that the bit stored at the address management circuitry has a second value indicating to associate an incoming memory address with the second node identifier; and associate the second request with the second node identifier in response to determining the bit stored has the second value.

7 . The system of claim 6 , wherein the address management circuitry is further configured to:
transmit, to the one or more nodes, a node identification value.

8 . The system of claim 7 , wherein the processor is further configured to:
receive data from a memory region in response to the address management circuitry transmitting the node identification value to the one or more nodes.

9 . The system of claim 1 , wherein the address management circuitry is further configured to:
associate the request with the first node identifier in response to determining the bit has the first value, wherein the address management circuitry is configured to transmit the request to the boot handler in response to associating the request with the first node identifier.

10 . A device comprising:
one or more logical components and a node identification table, wherein the one or more logical components are configured to:
receive a request associated with a boot process, the request identifying a memory address;
determine that a bit stored at the device has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process bypassing a second node identifier associated with nodes storing physical locations associated with the memory address of the request; and
associate the request with the first node identifier in response to determining the bit has the first value.

11 . The device of claim 10 , wherein the one or more logical components are configured to:
receive an indication to program the bit stored at the device to a second value indicating to associate an incoming memory address with the second node identifier associated with the nodes storing physical locations associated with the incoming memory addresses.

12 . The device of claim 10 , wherein the one or more logical components are configured to:
transmit the request with the first node identifier to logic at a first node coupled to the memory region, in response to determining the bit has the first value.

13 . The device of claim 10 , wherein the one or more logical components are configured to:
receive a second request from a processor; determine that the bit stored at address management circuitry has a second value indicating to associate the memory address with the second node identifier associated with the nodes storing physical locations corresponding to received memory addresses; and associate the second request with the second node identifier in response to determining that the bit stored has the second value.

14 . The device of claim 13 , wherein the one or more logical components are configured to:
transmit, to the nodes, a node identification value.

15 . The device of claim 10 , wherein the node identification table is to:
receive information corresponding to a table indicating one or more nodes storing physical locations associated with memory addresses, wherein the node identification table is to be programmed in response to receiving the information.

16 . A method, comprising:
receiving a request from a processor of a functional unit comprising the processor and address management circuitry, wherein the request comprises a memory address associated with a node storing physical locations associated with the memory address, wherein the request is associated with a boot process initialized at the processor; determining that a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process bypassing a second node storing physical locations associated with the memory address of the request; and transmitting the request with the first node identifier to logic at a first node coupled to the memory region in response to determining that the bit has the first value.

17 . The method of claim 16 , further comprising:
transmitting, to the processor, the data associated with the boot process from the memory region; and programming a node identification table of the address management circuitry in response to receiving the data.

18 . The method of claim 16 , further comprising:
receiving, at the processor, the data associated with the boot process from the memory region; erasing one or more caches in a system in response to receiving the data; and programming the bit to a second value to associate incoming memory addresses with a second node identifier associated with the second node storing physical locations associated with the incoming memory addresses, in response to erasing the one or more caches.

Assignees

• Mellanox Technologies Ltd

Inventors

• Rosenbluth Mark
• Xu Rui
• Orf Diane
• Cotsford Michael
• Tekade Shreya
• Woods David

Classifications

• G06F9/4403 Primary

  Processor initialisation · CPC title