Overflow event counter

Patent metadata

Field	Value
Publication number	US-12468534-B2
Application number	US-202318483699-A
Country	US
Kind code	B2
Filing date	Oct 10, 2023
Priority date	Oct 10, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A processing device comprises a register configured to store a count value indicating a number of times overflow events have resulted from arithmetic operations performed by the processing device. An execution unit of the device, in response to performing an arithmetic operation having a result which extends beyond one of the predefined limit values for the floating-point format, stores a result value that is within the predefined limit values, and cause the count value to be incremented. The count value provides a performant way of determining the number of overflow events that have occurred during the arithmetic processing performed by the execution unit. The count value provides a metric that provides a measure of the inaccuracy imparted into the results of the application processing by overflow events.

First claim

The invention claimed is:

1 . A processing device comprising:
an execution unit configured to execute instructions to perform arithmetic operations on input values represented according to a format, the format having a range of representable values extending between predefined limit values, the predefined limit values comprising a maximum positive value and a minimum negative value; and a first register configured to store a count value indicating a number of times overflow events have occurred when the processing device performs the arithmetic operations, wherein the execution unit is configured to, in response to performing a first of the arithmetic operations having a result which extends beyond one of the predefined limit values:
store a result value that is within the predefined limit values; and
cause the count value to be incremented.

2 . The processing device as claimed in claim 1 , wherein the stored result value is equal to one of the predefined limit values.

3 . The processing device as claimed in claim 1 , wherein each of the instructions is associated with a respective thread of a plurality of worker threads, wherein the execution unit is configured to, for each of the plurality of worker threads:
cause the count value to be incremented in response to a respective one of the arithmetic operations associated with the respective thread, the respective one of the arithmetic operations having a result which extends beyond one of the predefined limit values.

4 . The processing device as claimed in claim 3 , wherein the execution unit is further configured to interleave execution of a supervisor thread with the plurality of worker threads, wherein the first register is a status register of the supervisor thread.

5 . The processing device as claimed in claim 1 , wherein the format is a first floating-point format consisting of one of:
an 8-bit floating point format;
a 16-bit floating point format; and
a 32-bit floating point format.

6 . The processing device as claimed in claim 1 , wherein the execution unit is configured to:
execute further instructions to perform further arithmetic operations using values represented according to a further format, the further format having a further range of representable values extending between further predefined limit values; in response to performing a first of the further arithmetic operations having a further result which extends beyond one of the further predefined limit values:
store a further result value that is within the further predefined limit values; and
cause the count value to be incremented.

7 . The processing device as claimed in claim 6 , wherein the further format is a second floating point format consisting of one of:
an 8-bit floating point format; a 16-bit floating point format; and a 32-bit floating point format.

8 . The processing device as claimed in claim 1 , wherein the instructions are part of an application for performing training of a neural network.

9 . The processing device as claimed in claim 1 , comprising a second register, wherein the execution unit is configured to:
support a thread configured to write to the second register; and in response to the write to the second register, clear the count value.

10 . The processing device as claimed in claim 1 , comprising a third register,
wherein the execution unit is configured to: support a thread configured to write to the third register; and in response to the thread writing to the third register, enabling the incrementation of the count value in response to the arithmetic operations producing results which extend beyond the predefined limit values.

11 . A processing system comprising a plurality of instances of a processing device, each processing device comprising:
an execution unit configured to execute instructions to perform arithmetic operations on input values represented according to a format, the format having a range of representable values extending between predefined limit values; and a first register configured to store a count value indicating a number of times overflow events have occurred when the processing device performs the arithmetic operations, wherein the execution unit is configured to, in response to performing a first of the arithmetic operations having a result which extends beyond one of the predefined limit values:
store a result value that is within the predefined limit values; and
cause the count value to be incremented, wherein for each of the instances:
the execution unit of the respective instance is configured to cause a current value of the respective count value to be exported from the respective instance of the processing device.

12 . The processing system as claimed in claim 11 , comprising a further processing device comprising:
an interface configured to receive from each of the instances of the processing device, the respective count value for that instance; and at least one processor configured to sum the count values of the instances to determine a count of the number of overflow events in the processing system.

13 . The processing system as claimed in claim 12 , wherein the at least one processor is configured to compare the count of the number of overflow events in the processing system to a threshold.

14 . The processing system as claimed in claim 12 , wherein the further processing device is a host device.

15 . The processing system as claimed in claim 11 , wherein the plurality of instances of the processing device are configured to run an application to perform training of a neural network.

16 . A method comprising:
executing instructions to perform arithmetic operations on input values represented according to a format, the format having a range of representable values extending between predefined limit values, the predefined limit values comprising a maximum positive value and a minimum negative value; and storing in a first register, a count value indicating a number of times overflow events have occurred when the processing device performs the arithmetic operations, in response to performing a first of the arithmetic operations having a result which extends beyond one of the predefined limit values:
storing a result value that is within the predefined limit values; and
causing the count value to be incremented.

17 . A non-transitory computer readable medium storing a set of computer readable instructions, which when executed by at least one processor causes a method to be carried out, the method comprising:
executing instructions to perform arithmetic operations on input values represented according to a format, the format having a range of representable values extending between predefined limit values, the predefined limit values comprising a maximum positive value and a minimum negative value; and storing in a first register, a count value indicating a number of times overflow events have occurred when the processing device performs the arithmetic operations, in response to performing a first of the arithmetic operations having a result which extends beyond one of the predefined limit values:
storing a result value that is within the predefined limit values; and
causing the count value to be incremented.

Assignees

• Graphcore Ltd

Inventors

• Alexander Alan
• Masters Dominic

Classifications

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F7/4991

  Overflow or underflow · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title

• G06F9/321 Primary

  Program or instruction counter, e.g. incrementing · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title