Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip

Patent metadata

Field	Value
Publication number	US-12468375-B2
Application number	US-202318339422-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Jun 22, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising:
a plurality of processing devices each coupled to at least one power rail;
a plurality of local area management (LAM) circuits each assigned to one processing device of the plurality of processing devices, and each configured to, for its assigned processing device:
sample processing activity of the assigned processing device of a subset of the plurality of processing devices to generate a plurality of activity samples;
determine a current flow rate of the assigned processing device based on the plurality of activity samples;
determine whether the current flow rate of the assigned processing device exceeds a threshold current flow rate;
in response to determining the current flow rate of the assigned processing device exceeds the threshold current flow rate:
throttle the processing activity of the assigned processing device to throttle its power consumption;
estimate the power consumption of the assigned processing device based on the plurality of activity samples; and
generate an activity power event based on the estimated power consumption of the assigned processing device;
a plurality of regional area management (RAM) circuits each configured to:
receive a plurality of activity power events from a subset of LAM circuits of the plurality of LAM circuits; and
generate an aggregated activity power event based on the received plurality of activity power events from the subset of LAM circuits; and
a power estimation and limiting (PEL) circuit configured to:
receive a plurality of aggregated activity power events generated by the plurality of RAM circuits; and
generate a power limiting management response to cause the power consumption to be throttled in the IC chip based on the received plurality of aggregated activity power events.

2. The IC chip of claim 1 , wherein:
a processing device of the plurality of processing devices comprises a communication network.

3. The IC chip of claim 2 , wherein the plurality of processing devices further comprises a plurality of processing units and a plurality of supporting processing devices;
the plurality of processing units and the plurality of supporting processing devices coupled to the communication network; and
the plurality of processing units each configured to communicate to a supporting network device of the plurality of supporting processing devices over the communication network.

4. The IC chip of claim 3 , wherein:
the communication network comprises a plurality of network nodes; and
the communication network is configured to route communications from each processing unit of the plurality of processing units through one or more of the plurality of network nodes to a processing device of the plurality of processing devices.

5. The IC chip of claim 4 , wherein:
a LAM circuit of the plurality of LAM circuits is coupled to a network node of a subset of the plurality of network nodes assigned to the LAM circuit; and
the LAM circuit is configured to:
sample the processing activity of the assigned network node to generate a plurality of network activity samples;
determine a current flow rate of the assigned network node based on the plurality of network activity samples;
determine whether the current flow rate of the assigned network node exceeds the threshold current flow rate;
in response to determining the current flow rate of the assigned network node exceeds the threshold current flow rate:
throttle the processing activity of the assigned network node to throttle its power consumption;

estimate the power consumption of the assigned network node based on the plurality of network activity samples; and
generate the activity power event based on the estimated power consumption of the assigned network node.

6. The IC chip of claim 5 , wherein the LAM circuit is configured to throttle the processing activity of the assigned network node to throttle its power consumption by being configured to selectively enable and disable communication flow of the assigned network node.

7. The IC chip of claim 6 , wherein the LAM circuit is configured to selectively enable and disable the communication flow in the assigned network node by being configured to selectively generate enable and disable throttle signals that cause the assigned network node to selectively enable and disable, respectively, communication flow in the assigned network node.

8. The IC chip of claim 3 , further comprising:
a clock circuit configured to generate a clock signal to clock the plurality of processing units;
wherein:
the PEL circuit is further configured to determine a clock throttling of the clock circuit, to clock throttle power consumption of the plurality of processing units based on the received plurality of aggregated activity power events; and
the PEL circuit is configured to, in response to determining the clock throttling for the clock circuit:
generate the power limiting management response by being configured to generate a clock throttling power limiting management response to throttle the clock signal.

9. The IC chip of claim 1 , wherein:
the plurality of processing devices comprises a plurality of processing units;
a LAM circuit of the plurality of LAM circuits is coupled to a processing unit of a subset of the plurality of processing units assigned to the LAM circuit; and
the LAM circuit is configured to:
sample the processing activity of the assigned processing unit to generate a plurality of processing unit activity samples;
determine a current flow rate of the assigned processing unit based on the plurality of processing unit activity samples;
determine whether the current flow rate of the assigned processing unit exceeds the threshold current flow rate;
in response to determining the current flow rate of assigned processing unit exceeds the threshold current flow rate:
throttle the processing activity of the assigned processing unit to throttle its power consumption;

estimate the power consumption of the assigned processing unit based on the plurality of processing unit activity samples; and
generate the activity power event based on the estimated power consumption of the assigned processing unit.

10. The IC chip of claim 1 , wherein one or more processing devices of the plurality of processing devices are coupled to at least two power rails.

11. The IC chip of claim 1 , wherein each LAM circuit of the plurality of LAM circuits is configured to sample the processing activity of a single processing device of the subset of the plurality of processing devices to generate the plurality of activity samples.

12. The IC chip of claim 1 , wherein each LAM circuit of the plurality of LAM circuits comprises:
an accumulate circuit configured to, for each activity sample of the plurality of activity samples:
correlate the received activity sample into a next incoming estimated current demand; and
accumulate the next estimated incoming current demand into a next estimated current demand; and

a di/dt circuit configured to:
compare the next estimated current demand to a previous estimated current demand to generate a next current flow rate of the assigned processing device;

wherein the LAM circuit is configured to:
determine whether the next current flow rate of the assigned processing device exceeds the threshold current flow rate; and
in response to determining the next current flow rate of the assigned processing device exceeds the threshold current flow rate:
throttle the processing activity of the assigned processing device to throttle its power consumption.

13. The IC chip of claim 12 , w

Assignees

• Qualcomm Inc

Inventors

• Chamarty Vinod
• KOORAPATI Sagar
• Naveh Alon

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• H04W52/0251

  using monitoring of local events, e.g. events related to user activity · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title