Diagnostic ring oscillator circuit for DC and transient characterization

Patent metadata

Field	Value
Publication number	US-12467974-B2
Application number	US-202318396111-A
Country	US
Kind code	B2
Filing date	Dec 26, 2023
Priority date	Aug 28, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Methods and apparatus for a diagnostic in situ ring oscillator (RO) circuit for DC and transient characterization. The RO circuit includes a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, where each stage includes a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of a CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage. The first stage is a configurable enable stage to enable the inverter chain to be set into a defined logic state, followed by multiple pre-stage-DUT stages. The output of the last stage is feed back to the input of the enable stage to form an RO feedback signal. The RO circuit can operate in multiple modes including an AC mode, a DC mode, and a hybrid mode.

First claim

What is claimed is:

1 . An in situ ring oscillator (RO) circuit for capturing one or more characteristic relating to aging of CMOS circuitry in a CMOS device, comprising:
a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, the plurality of symmetrical stages including, for each stage, a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between first and second power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of the CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage; wherein the plurality of symmetrical stages include at least:
an enable stage configured to enable the inverter chain to be put into a defined logic state or mode;
one or more Device Under Test (DUT) stages, each having a gate of the first power-gating transistor coupled to a DUT header, and a gate of the second power-gating transistor coupled to a DUT footer; and
a pre-stage, preceding each of the one or more DUT stages.

2 . The in situ RO circuit of claim 1 , further comprising a plurality of header devices and footer devices coupled to the gates of the first and second power-gating transistors, wherein the plurality of header devices and footer devices enable configuration of the RO circuit to enable a dynamic aging mode and a static aging mode, and wherein in the static aging mode, a first DUT stage can be put in either Negative Bias Temperature Instability (NBTI)/nMOS Non-Conducting Stress (NCS) stress mode or Positive Bias Temperature Instability PBTI/pMOS NCS stress mode.

3 . The in situ RO circuit of claim 2 , wherein the first DUT stage includes a CMOS inverter circuit comprising a thin oxide pMOS transistor and a thin oxide nMOS transistor and wherein the RO circuit is configurable to perform dynamic and static RO stress testing of the thin oxide pMOS transistor and the thin oxide nMOS transistor.

4 . The in situ RO circuit of claim 2 , wherein the first DUT stage includes a CMOS inverter circuit comprising a thick oxide pMOS transistor and a thick oxide nMOS transistor and wherein the RO circuit is configurable to perform dynamic and static RO stress testing of the thick oxide pMOS transistor and the thick oxide nMOS transistor.

5 . The in situ RO circuit of claim 1 , further comprising:
a pass gate circuit coupled between a static bias device and the RO feedback signal line comprising a pMOS transistor and an nMOS transistor arranged in parallel to the PMOS transistor; and control inputs respectively coupled to the gate of the pMOS transistor and the gate of the nMOS transistor, wherein the control inputs can be used to selectively couple the static bias device to the RO feedback signal line.

6 . The in situ RO circuit of claim 1 , further comprising:
a pass gate circuit coupled between a gate force device and the RO feedback signal line comprising a pMOS transistor and an nMOS transistor arranged in parallel to the PMOS transistor; and control inputs respectively coupled to the gate of the pMOS transistor and the gate of the nMOS transistor, wherein the control inputs can be used to selectively couple the gate force device to the RO feedback signal line.

7 . The in situ RO circuit of claim 1 , further comprising:
a first pass gate circuit coupled between a drain force device and the RO feedback signal line comprising a first pMOS transistor and a first nMOS transistor arranged in parallel to the first PMOS transistor; a second pass gate circuit coupled between a drain sense device and the RO feedback signal line comprising a second pMOS transistor and a second nMOS transistor arranged in parallel to the second PMOS transistor; and control inputs respectively coupled to gates of the first and second pMOS transistors and to gates of the first and second nMOS transistors, wherein the control inputs can be used to selectively couple the drain force device to the RO feedback signal line and to selectively couple the drain sense device to the RO feedback signal line.

8 . The in situ RO circuit of claim 1 , further comprising a plurality of duty cycle circuits, between each of the plurality of symmetrical stages including the RO feedback signal line, wherein the RO circuit is configurable to enable measurement of a duty cycle during stress testing of the pMOS and nMOS transistors in one or more DUT stage CMOS inverters.

9 . The in situ RO circuit of claim 8 , further comprising a duty cycle pad coupled to a first duty cycle circuit, wherein the first duty cycle circuit is configured to infer the duty cycle of a stage by measuring circuit output voltage.

10 . The in situ RO circuit of claim 1 , wherein each DUT stage is preceded by the pre-stage including a means for selectively coupling a gate force to the RO feedback signal line prior to an input of the CMOS inverter for the DUT stage.

11 . A CMOS device, comprising:
CMOS circuitry configured to perform at least one function and including a plurality of pMOS and nMOS transistors; and an in situ ring oscillator (RO) circuit, including:
a plurality of symmetrical stages coupled via an RO feedback signal line, the plurality of symmetrical stages including, for each stage, a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between first and second power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of the CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage;
wherein the plurality of symmetrical stages include at least:
a configurable enable stage configured to enable an inverter chain to be set into a defined logic state;
one or more Device Under Test (DUT) stages, each having a gate of the first power-gating transistor coupled to a DUT header, and a gate of the second power-gating transistor coupled to a DUT footer; and
a pre-stage, preceding each of the one or more DUT stages; and
wherein the pair of pMOS and nMOS transistors in the CMOS inverter of the plurality of symmetrical stages comprise a portion of the plurality of pMOS and nMOS transistors of the CMOS circuitry.

12 . The CMOS device of claim 11 , further comprising a plurality of header devices and footer devices coupled to the gates of the first and second power-gating transistors, wherein the plurality of header devices and footer devices enable configuration of the RO circuit to enable a dynamic aging mode and a static aging mode, and wherein in the static aging mode a DUT stage can be put in either Negative Bias Temperature Instability (NBTI)/nMOS Non-Conducting Stress (NCS) stress mode or Positive Bias Temperature Instability PBTI/pMOS NCS stress mode.

13 . The CMOS device of claim 11 , further comprising:
means for configuring the RO circuit to operate in a DC-Static mode to enable measurements of pMOS and nMOS transistor I/V (current-voltage) characteristics.

14 . The CMOS device of claim 11 , further comprising:
means for configuring the RO circuit to operate in an AC-Closed Loop mode to enable measurement frequency and in situ duty cycle.

15 . The CMOS device of claim 11 , further comprising:
means for configuring the RO circuit to operate in a hybrid AC-Open Loop or DC-Static mode to enable study of pMOS and nMOS transistor zero Hz and low frequency phenomena.

16 . A method for in situ testing a CMOS device comprising a plurality of pMOS and nMOS transistors, comprising:
applying control and voltage inputs to a ring oscillator (RO) circuit, having a plurality of symmetrical stages co

Assignees

• Intel NDTM US LLC

Inventors

• Kerber Andreas
• Kliza Phillip

Classifications

• H03K3/354

  Astable circuits · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• G01R31/2626

  for measuring noise (measuring noise factor in general G01R29/26) · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title