Measurement system and testing method of testing a device under test

Patent metadata

Field	Value
Publication number	US-12467829-B2
Application number	US-202218050383-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Oct 27, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A measurement system includes a common port, the common port being connectable to a signal output of the device under test. The measurement system further includes a signal line being connected to the common port, wherein the signal line includes a first directional coupler portion and a second directional coupler portion. The measurement system further includes a signal processing circuit, wherein the signal processing circuit includes an IQ analysis circuit and an IQ synthesizer circuit. The IQ analysis circuit is connected with the common port via the first directional coupler portion so as to receive a forward-travelling signal from the common port. Further, a testing method of testing a device under test is described.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1 . A measurement system for testing a device under test, the measurement system comprising
a common port configured to be connectable to a signal output of the device under test, wherein the device under test comprises electronic circuitry configured to generate an IQ data signal as an output signal or to process an IQ data signal to obtain the output signal; a signal line connected to the common port, wherein the signal line comprises a first directional coupler portion and a second directional coupler portion; a signal processing circuit, wherein the signal processing circuit comprises an IQ analysis circuit, an IQ synthesizer circuit, and a control circuit; wherein the IQ analysis circuit is connected with the common port via the first directional coupler portion so as to receive a forward-travelling signal from the common port, wherein the IQ analysis circuit is configured to determine IQ data associated with the forward-travelling signal, wherein the IQ synthesizer circuit is connected to the signal line, wherein the IQ synthesizer circuit is configured to generate a backward-travelling signal that is forwarded to the common port, wherein the IQ analysis circuit is further connected with the signal line via the second directional coupler portion so as to receive the backward-travelling signal, wherein the IQ analysis circuit is configured to determine IQ data associated with the backward-travelling signal, and wherein the control circuit is configured to control the IQ synthesizer circuit such that a predefined reflection coefficient is obtained, wherein the predefined reflection coefficient corresponds to a ratio of the backward-travelling signal and the forward-travelling signal.

2 . The measurement system of claim 1 , wherein the backward-travelling signal is an IQ data stream.

3 . The measurement system of claim 1 , wherein the control circuit is configured to control the IQ synthesizer circuit to iteratively adapt the backward-travelling signal, such that the predefined reflection coefficient is obtained.

4 . The measurement system of claim 3 , wherein the forward-travelling signal is periodic for at least a predetermined number of iterations.

5 . The measurement system of claim 1 , wherein the predefined reflection coefficient is determined based on a desired impedance that is to be applied to the device under test.

6 . The measurement system of claim 5 , wherein the predefined reflection coefficient is determined based on the desired impedance and based on a characteristic impedance of the measurement system.

7 . The measurement system of claim 6 , wherein the predefined reflection coefficient is determined according to K=(Z T −Z 0 *)/(Z T +Z 0 ), wherein K is the predefined reflection coefficient, Z T is the desired impedance, and Z 0 is the characteristic impedance.

8 . The measurement system of claim 1 , wherein the IQ analysis circuit is configured to analyze the output signal of the device under test after the predefined reflection coefficient is obtained, thereby obtaining at least one performance parameter of the device under test.

9 . The measurement system of claim 8 , wherein the at least one performance parameter comprises an error vector magnitude (EVM) and/or an adjacent channel leakage ratio (ACLR).

10 . The measurement system of claim 8 , wherein the at least one performance parameter is determined for at least one further predefined reflection coefficient, for a different DUT input power, a different DUT output power, and/or a different frequency of the forward-travelling signal.

11 . The measurement system of claim 1 , wherein IQ data associated with the forward-travelling signal and the IQ data associated with the backward-travelling signal are determined in time domain.

12 . The measurement system of claim 1 , wherein the backward-travelling signal is generated in time domain.

13 . The measurement system of claim 1 , wherein the forward-travelling signal is a single carrier orthogonal frequency division multiplexing (OFDM) signal.

14 . The measurement system of claim 1 , wherein the IQ analysis circuit is configured to determine the IQ data associated with the forward-travelling signal and/or the IQ data associated with the backward-travelling signal in absence of a reference signal.

15 . The measurement system of claim 1 , wherein the IQ analysis circuit is configured to mix the forward-travelling signal with a local oscillator signal in the analog domain or in the digital domain in order to determine the IQ data associated with the forward-travelling signal,
and/or wherein the IQ analysis circuit is configured to mix the backward-travelling signal with a local oscillator signal in the analog domain or in the digital domain in order to determine the IQ data associated with the backward-travelling signal.

16 . The measurement system of claim 1 , wherein the IQ synthesizer circuit comprises a digital-to-analog converter for generating the backward-travelling signal.

17 . A testing method of testing a device under test, the testing method comprising the steps of:
receiving, by a common port, an output signal of the device under test, wherein the device under test comprises electronic circuitry configured to generate an IQ data signal as the output signal or to process an IQ data signal to obtain the output signal; forwarding, by a first directional coupler portion, a forward-travelling signal corresponding to the output signal to an IQ analysis circuit of a signal processing circuit; determining, by the IQ analysis circuit, IQ data associated with the forward-travelling signal; generating, by an IQ synthesizer circuit, a backward-travelling signal; forwarding, by a second directional coupler portion, the backward-travelling signal to the IQ analysis circuit; determining, by the IQ analysis circuit, IQ data associated with the backward-travelling signal; and controlling, by a control circuit, the IQ synthesizer circuit such that a predefined reflection coefficient is obtained, wherein the predefined reflection coefficient corresponds to a ratio of the backward-travelling signal and the forward-travelling signal.

18 . The testing method of claim 17 , wherein the backward-travelling signal is iteratively adapted such that a predefined reflection coefficient is obtained, wherein the predefined reflection coefficient corresponds to a ratio of the backward-travelling signal and the forward-travelling signal.

19 . The testing method of claim 17 , wherein all steps are performed in time domain.

20 . A measurement system for testing a device under test, the measurement system comprising
a common port configured to be connectable to a signal output of the device under test, wherein the device under test comprises electronic circuitry configured to generate an IQ data signal as an output signal or to process an IQ data signal to obtain the output signal; a signal line connected to the common port, wherein the signal line comprises a first directional coupler portion and a second directional coupler portion; and a signal processing circuit, wherein the signal processing circuit comprises an IQ analysis circuit and an IQ synthesizer circuit; wherein the IQ analysis circuit is connected with the common port via the first directional coupler portion so as to receive a forward-travelling signal from the common port, wherein the IQ anal

Assignees

• Rohde & Schwarz

Inventors

• Lloyd Paul Gareth

Classifications

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G01R27/28

  Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response (in line transmission systems H04B3/46) · CPC title

• G01M99/005 Primary

  Testing of complete machines, e.g. washing-machines or mobile phones (testing of machine parts G01M13/00; testing of electric apparatus or components G01R31/50) · CPC title

• G01R27/32 Primary

  in circuits having distributed constants {, e.g. having very long conductors or involving high frequencies} · CPC title