Analog-to-digital converter and thermopile array

Patent metadata

Field	Value
Publication number	US-12467793-B2
Application number	US-202117796952-A
Country	US
Kind code	B2
Filing date	May 27, 2021
Priority date	Sep 22, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.

First claim

What is claimed is:

1 . A thermopile array, comprising:
a plurality of sensor pixel cells; and a readout integrated circuit (ROIC) including multiple signal processing channels, each of the signal processing channels including: a pre-amplifier configured to amplify a sensor signal, the pre-amplifier being a single-stage amplifier; and an analog-to-digital converter (ADC) having an input terminal coupled to an output terminal of the pre-amplifier, the ADC being a delta-sigma ADC and including a reference voltage generation circuit; wherein the reference voltage generation circuit includes: a voltage generation unit; a chopping modulation unit configured to perform chopping modulation on a voltage signal generated by the voltage generation unit, and modulate low-frequency noise of the voltage signal into high-frequency noise; and a low-pass filter configured to eliminate the high-frequency noise to obtain a reference voltage; and wherein each of the signal processing channels is configured to process the sensor signals output by i sensor pixel cells, where i is a positive integer, and when the number of the plurality of sensor pixel cells is no less than 256, i is no greater than the number of the sensor pixel cells of the thermopile array divided by 4 after extraction of root; and wherein no low-pass filter is arranged between the ADC and the pre-amplifier of each of the signal processing channels.

2 . The thermopile array according to claim 1 , wherein the multiple signal processing channels and the plurality of sensor pixel cells are identical in number, and the signal processing channels are in one-to-one correspondence to the sensor pixel cells; or the thermopile array further includes at least one multiplexer (MUX), each MUX has an input terminal coupled to one or more of the sensor pixel cells and an output terminal coupled to one of the signal processing channels, and different MUXs are coupled to different signal processing channels; and
wherein the sensor pixel cells coupled to a single MUX are simultaneously switched on or simultaneously switched off, so that the sensor signals of the sensor pixel cells switched on are combined together and sent to the coupled signal processing channel.

3 . The thermopile array according to claim 1 , wherein the pre-amplifier adopts a chopper-stabilized modulation mode.

4 . The thermopile array according to claim 1 , wherein at most 8 sensor pixel cells are coupled to one signal processing channel through one MUX.

5 . The thermopile array according to claim 1 , wherein the sensor pixel cells are arranged to form a sensor array, and the number of the signal processing channels is at least 4 times the number of rows of the sensor array.

6 . The ADC according to claim 1 , wherein the voltage generation unit is a bandgap voltage reference (BGR); or
an operating power supply voltage of the ADC is less than 1.2 V, the ADC includes a bipolar junction transistor (BJT), and Vbe of the BJT serves as the voltage signal generated by the voltage generation unit.

7 . The ADC according to claim 1 , wherein a cut-off frequency of the low-pass filter is no higher than 100 Hz.

8 . The ADC according to claim 1 , wherein the low-pass filter includes a resistor unit and a filter capacitor, and the resistor unit includes a switch capacitor circuit.

9 . The ADC according to claim 1 , wherein the reference voltage generated by the reference voltage generation circuit includes a positive reference voltage and a negative reference voltage, and a voltage difference between the positive reference voltage and the negative reference voltage is adjustable in a range from ±50 mV to ±200 mV, so as to adjust a dynamic input range of the ADC.

10 . The ADC according to claim 1 , further comprising a dithering signal generation unit configured to generate a dithering signal at a preset frequency and output the dithering signal to an input terminal of the ADC.

11 . The ADC according to claim 1 , wherein the ADC is of a first-order single-bit quantizer feedback structure.

12 . The ADC according to claim 11 , wherein an oversampling rate of the ADC is greater than 4096, and an integrator in the ADC is an inverter-type integrator.

13 . The ADC according to claim 1 , wherein the ADC includes a capacitor having a unit capacitance of not greater than 100 fF.

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Li Chen
• Wang Hao

Classifications

• G01J2005/202

  Arrays · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/34

  by chopping · CPC title

• H03M3/328

  using dither · CPC title

• G01J2005/123

  Thermoelectric array · CPC title