Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12464910-B2
Application number	US-202117789153-A
Country	US
Kind code	B2
Filing date	Aug 12, 2021
Priority date	Sep 11, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Provided in the present disclosure are a display substrate and a display device. In the display substrate, at least a portion of a cathode is located in a display region; at least one driver chip is located in a non-display region; a first power supply signal line pattern is located in the non-display region and arranged on at least one side of the display region. The first power supply signal line pattern comprises a first transmission portion and a first wire inlet portion electrically connected to the first transmission portion. The first transmission portion extends in a first direction, and is electrically connected to the cathode. The first wire inlet portion extends in a second direction intersecting with the first direction. The first wire inlet portion is electrically connected to the at least one driver chip.

First claim

What is claimed is:

1 . A display substrate, comprising: a display area and a non-display area surrounding the display area; the display substrate further comprising a cathode, a first power signal line pattern and at least one driver chip;
wherein at least a portion of the cathode is located in the display area; the at least one driver chip is located in the non-display area; and the first power signal line pattern is located in the non-display area and is located on at least one side of the display area, and the first power signal line pattern comprises a first transmission portion and a first incoming line portion electrically connected to the first transmission portion; and the first transmission portion extends in a first direction, the first transmission portion is electrically connected to the cathode, the first incoming line portion extends in a second direction intersecting with the first direction, and the first incoming line portion is electrically connected to the at least one driver chip; wherein the display substrate further comprises a second power signal line pattern, and the second power signal line pattern comprises a first sub-pattern and a plurality of second sub-patterns; the first sub-pattern comprises a second transmission portion, and two second incoming line portions electrically connected to the second transmission portion, the two second incoming line portions are electrically connected to the at least one driver chip, and the first power signal line pattern is located between the two second incoming line portions; the plurality of second sub-patterns is located in the display area, and the plurality of second sub-patterns is electrically connected to the second transmission portion; and the second power signal line pattern is configured to transmit a positive power signal.

2 . The display substrate according to claim 1 , wherein the at least one driver chip is located at a first side of the display area, and the first power signal line pattern is located between the display area and the at least one driver chip; and the first power signal line pattern is configured to transmit a negative power signal.

3 . The display substrate according to claim 1 , wherein the display area comprises a plurality of data lines and a plurality of sub-pixels, and the plurality of data lines is electrically connected to the plurality of sub-pixels; the non-display area comprises a fan-out region and a driver chip bonding region, wherein the fan-out region is located between the display area and the driver chip bonding region;
the fan-out region comprises a plurality of fan-out lines, at least one of the fan-out lines is an integral structure, and first ends of the plurality of fan-out lines are connected to the plurality of data lines; and the at least one driver chip is arranged in the driver chip bonding region, and second ends of the plurality of fan-out lines are connected to first pins included in the at least one driver chip.

4 . The display substrate according to claim 3 , wherein the plurality of fan-out lines is arranged in the same layer and made of the same material.

5 . The display substrate according to claim 3 , wherein the plurality of fan-out lines comprise a plurality of first fan-out lines and a plurality of second fan-out lines, the plurality of first fan-out lines is arranged in the same layer and made of the same material, and the plurality of second fan-out lines is arranged in the same layer and made of the same material; the plurality of first fan-out lines and the plurality of second fan-out lines are arranged in different layers; and orthographic projections of the plurality of first fan-out lines onto a base of the display substrate and orthographic projections of the plurality of second fan-out lines onto the base are alternately arranged.

6 . The display substrate according to claim 3 , wherein the fan-out region and the driver chip bonding region are both located at a first side of the display area; and
the non-display area is provided with an electrostatic discharge circuit, and the electrostatic discharge circuit is located at a second side of the display area, the first side is opposite to the second side.

7 . The display substrate according to claim 3 , wherein the first power signal line pattern and the second power signal line pattern are arranged in the same layer, and the first power signal line pattern is insulated from the second power signal line pattern.

8 . The display substrate according to claim 7 , wherein the display substrate further comprises an insulating layer, and in a direction perpendicular to the base of the display substrate, the first power signal line pattern and the second power signal line pattern are located at the same side of the insulating layer, and the plurality of fan-out lines is located at the other side of the insulating layer; and
an orthographic projection of the first power signal line pattern onto the base of the display substrate at least partially overlaps with orthographic projections of the plurality of fan-out lines onto the base; and/or an orthographic projection of the second power signal line pattern onto the base at least partially overlaps with the orthographic projections of the plurality of fan-out lines onto the base.

9 . The display substrate according to claim 7 , wherein the orthographic projection of the first power signal line pattern onto the base of the display substrate does not overlap with the orthographic projections of the plurality of fan-out lines onto the base.

10 . The display substrate according to claim 3 , wherein the display substrate further comprises a sub-pixel driver circuit, the sub-pixel driver circuit comprises:
an active layer, a first gate metal layer and a first source-drain metal layer which are stacked in the sequence listed in a direction away from the base of the display substrate; and the plurality of fan-out lines and the first source-drain metal layer are arranged in the same layer and made of the same material, and the first power signal line pattern and the second power signal line pattern are both arranged in the same layer and made of the same material as the first gate metal layer.

11 . The display substrate according to claim 3 , wherein the display substrate further comprises a sub-pixel driver circuit, the sub-pixel driver circuit comprises:
an active layer, a first gate metal layer and a first source-drain metal layer which are stacked in the sequence listed in a direction away from the base of the display substrate; and the plurality of fan-out lines and the first gate metal layer are arranged in the same layer and made of the same material, and the first power signal line pattern and the second power signal line pattern are both arranged in the same layer and made of the same material as the first source-drain metal layer.

12 . The display substrate according to claim 3 , wherein
the plurality of fan-out lines is grouped into at least one fan-out line set which is in one-to-one correspondence with the at least one driver chip, a fan-out line set in the at least one fan-out line set is of a fan shape, and second ends of fan-out lines included in the fan-out line set are connected to first pins included in a corresponding driver chip in one-to-one correspondence.

13 . A display device, comprising a display substrate, wherein the display substrate comprises a display area and a non-display area surrounding the display area; the display substrate further comprises a cathode, a first power signal line pattern and at least one driver chip;
wherein at least a portion of the cathode is locate

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Wang Guoying
• Lin Yicheng
• Han Ying
• Chu Mingi
• Xu Pan
• Zhang Xing

Classifications

• H10K59/12

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K59/80522

  combined with auxiliary electrodes · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• G09F9/30

  in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title