Method of manufacturing semiconductor devices and semiconductor devices

Patent metadata

Field	Value
Publication number	US-12464814-B2
Application number	US-202217862801-A
Country	US
Kind code	B2
Filing date	Jul 12, 2022
Priority date	May 11, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure; forming an isolation insulating layer so that the stacked layer is exposed from the isolation insulating layer; forming a sacrificial cladding layer over at least sidewalls of the exposed stacked layer; forming a sacrificial gate electrode over the exposed stacked layer; forming an interlayer dielectric (ILD) layer over the exposed stacked layer; partially recessing the sacrificial gate electrode to leave a pillar of a remaining sacrificial gate electrode; removing the sacrificial cladding layer and the first semiconductor layers; forming a gate dielectric layer wrapping around the second semiconductor layers and a gate electrode over the gate dielectric layer; removing the pillar; and forming one or more dielectric layers in a space from which the pillar is removed.

2 . The method of claim 1 , wherein the first semiconductor layers are made of SiGe and the second semiconductor layers are made of Si.

3 . The method of claim 2 , wherein the sacrificial cladding layer is made of SiGe.

4 . The method of claim 3 , wherein the sacrificial cladding layer is amorphous or polycrystalline.

5 . The method of claim 1 , wherein the fin structure further includes a first insulating liner layer on a top of the stacked layer and a top semiconductor layer on the first insulating liner layer.

6 . The method of claim 5 , wherein the top semiconductor layer is made of SiGe.

7 . The method of claim 5 , wherein before the sacrificial cladding layer is formed, a second insulating liner layer is formed.

8 . The method of claim 5 , wherein the sacrificial gate electrode is recessed to a level between a bottom of the top semiconductor layer and a top of the top semiconductor layer.

9 . A method of manufacturing a semiconductor device, comprising:
forming first and second fin structures, each including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer; forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer; forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer; forming a sacrificial gate electrode over the exposed stacked layer of the first and second fin structures; forming a source/drain epitaxial layer over source/drain regions of the first and second fin structures; forming an interlayer dielectric (ILD) layer over the source/drain epitaxial layer; partially recessing the sacrificial gate electrode to leave a pillar of a remaining sacrificial gate electrode between the first and second fin structures; removing the sacrificial cladding layer and the first semiconductor layers from the first and second fin structures; forming a gate dielectric layer wrapping around the second semiconductor layers of the first and second fin structures; forming a first gate electrode over the bottom fin structure of the first fin structure and a second gate electrode over the bottom fin structure of the second fin structure; removing the pillar; and forming a gate separation wall including one or more dielectric layers in a space from which the pillar is removed.

10 . The method of claim 9 , wherein the gate separation wall includes a first insulating layer and a second insulating layer made of a different material from the first insulating layer.

11 . The method of claim 10 , wherein the first insulating layer is in direct contact with the first gate electrode and the second gate electrode.

12 . The method of claim 10 , further comprising forming a top gate electrode over the first gate electrode and the second gate electrode.

13 . The method of claim 12 , further comprising:
forming an opening in the top gate electrode to separate the top gate electrode; and filling the opening with an insulating material.

14 . The method of claim 13 , wherein after separating, the top gate electrode is in contact with at least one of the first insulating layer or the second insulating layer of the gate separation wall.

15 . The method of claim 10 , wherein:
the source/drain epitaxial layer formed at the source/drain regions of the first fin structure and the source/drain epitaxial layer formed at the source/drain regions of the second fin structure are separated by an epitaxial layer separation structure, and the epitaxial layer separation structure includes a first dielectric layer in direct contact with the source/drain epitaxial layer and a second dielectric layer made of a different material than the first dielectric layer.

16 . The method of claim 15 , wherein the first insulating layer of the gate separation wall and the first dielectric layer of the epitaxial layer separation structure are made of different materials from each other.

17 . The method of claim 15 , wherein the second insulating layer of the gate separation wall and the second dielectric layer of the epitaxial layer separation structure are made of different materials from each other.

18 . A semiconductor device comprising:
a first gate-all-around field effect transistor (GAA FET) and a second GAA FET; and a gate separation wall disposed between the first GAA FET and the second GAA FET and disposed on an isolation insulating layer, wherein: the gate separation wall includes a first dielectric layer and a second dielectric layer embedded in the first dielectric layer, and a gate electrode of at least one of the first GAA FET or the second GAA FET is in contact with an upper surface of the gate separation wall.

19 . The semiconductor device of claim 18 , wherein a gate electrode of the first GAA FET and a gate electrode of the second GAA FET are discontinuous.

20 . The semiconductor device of claim 18 , wherein the first dielectric layer is in direct contact with a side of a gate electrode of the first GAA FET and a gate electrode of the second GAA FET.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Kuan-Ting
• Chiang Kuo-Cheng
• Ju Shi Ning
• Jihan Yi-Ruei
• Wang wei ting
• Wang Chih-Hao

Classifications

• H10D84/0179

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title