Transistor with controllable source/drain structure

Patent metadata

Field	Value
Publication number	US-12464782-B2
Application number	US-202217751727-A
Country	US
Kind code	B2
Filing date	May 24, 2022
Priority date	Jul 23, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

First claim

What is claimed is:

1 . A transistor structure comprising:
a substrate; a gate conductive region, at least a portion of the gate conductive region disposed below a surface of the substrate; a gate dielectric layer surrounding a bottom wall and sidewalls of the gate conductive region; and a first conductive region; wherein a bottom wall of the first conductive region is aligned with a top wall of the gate conductive region, and the first conductive region includes an epitaxial semiconductor layer extending upward from the bottom wall of the first conductive region.

2 . The transistor structure according to claim 1 , wherein the top wall of the first conductive region is aligned or substantially aligned with a top wall of a shallow trench isolator (STI) region next to the first conductive region, but lower than a top wall of a gate cap layer on the gate conductive region.

3 . The transistor structure according to claim 1 , wherein a doping concentration from the bottom wall of the first conductive region to a top wall of the first conductive region is adjustable.

4 . The transistor structure according to claim 3 , wherein the first conductive region with the adjustable doping concentration is independent from the substrate.

5 . The transistor structure according to claim 4 , wherein the substrate is a silicon substrate, and the first conductive region with the adjustable doping concentration is formed by a selective growth process.

6 . The transistor structure according to claim 1 , further comprising a channel layer surrounding the gate dielectric layer, wherein the channel layer is independent from the substrate.

7 . The transistor structure according to claim 6 , wherein the channel layer is a doped silicon layer.

8 . The transistor structure according to claim 6 , wherein the channel layer is a doped silicon-germanium (Si 1-x Ge x ) layer.

9 . The transistor structure according to claim 6 , wherein the substrate is a silicon substrate, and the channel layer is formed by a selective growth process.

10 . The transistor structure according to claim 1 , further comprising a channel layer surrounding the gate dielectric layer, wherein the channel layer is a doped layer within the substrate.

11 . A transistor structure comprising:
a substrate; a gate conductive region, at least a portion of the gate conductive region disposed below a surface of the substrate; a gate dielectric layer surrounding a bottom wall and sidewalls of the gate conductive region; and a first conductive region; wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region; wherein the gate dielectric layer includes a horizontal extension portion covering a top wall of the first conductive region.

12 . The transistor structure according to claim 11 , a top surface of one terminal of the channel layer is aligned or substantially aligned with the surface of the substrate.

13 . The transistor structure according to claim 11 , wherein the gate conductive region includes a tungsten plug and a titanium nitride (TiN) layer surrounding the tungsten plug.

14 . A transistor structure comprising:
a substrate; a gate conductive region, at least a portion of the gate conductive region disposed below a surface of the substrate; a gate dielectric layer surrounding a bottom wall and sidewalls of the gate conductive region; and a first conductive region adjacent to the gate conductive region and independent from the substrate; wherein a distance of a vertical gap or a vertical overlap between a bottom wall of the first conductive region and a top wall of the gate conductive region is smaller than 5 nm, and the first conductive region includes an epitaxial semiconductor layer extending upward from the bottom wall of the first conductive region.

15 . The transistor structure according to claim 14 , wherein a doping concentration from the bottom wall of the first conductive region to a top wall of the first conductive region is vertically adjustable.

16 . The transistor structure according to claim 15 , wherein the substrate is a silicon substrate, and the first conductive region with the vertically adjustable doping concentration is formed by a selective growth process.

17 . A transistor structure comprising:
a substrate; a gate conductive region, at least a portion of the gate conductive region disposed below a surface of the substrate; a gate dielectric layer surrounding a bottom wall and sidewalls of the gate conductive region; a channel layer surrounding the gate dielectric layer; and a first conductive region contacted to the channel layer; wherein the channel layer is a composite layer and independent from the substrate.

18 . The transistor structure according to claim 17 , wherein the composite layer includes a high mobility sublayer and a silicon sublayer over the high mobility sublayer.

19 . The transistor structure according to claim 18 , wherein the high mobility sublayer is a doped Si 1-x Ge x , Si 1-x C x , Ga 1-x As x , or In 1-x As x Sb layer.

20 . A transistor structure comprising:
a substrate; a gate conductive region, at least a portion of the gate conductive region disposed below a surface of the substrate; a gate dielectric layer surrounding a bottom wall and sidewalls of the gate conductive region; and a first conductive region; wherein a top wall of the first conductive region is lower than a top wall of a shallow trench isolator (STI) region next to the first conductive region, and lower than a top wall of a gate cap layer on the gate conductive region.

21 . The transistor structure according to claim 20 , wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Assignees

• Invent And Collaboration Laboratory Pte Ltd
• Etron Tech Inc

Inventors

• Lu chao-chun
• Huang Li-Ping

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/637

  Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title