Stacked high-blocking InGaAs semiconductor power diode

Patent metadata

Field	Value
Publication number	US-12464741-B2
Application number	US-202117209151-A
Country	US
Kind code	B2
Filing date	Mar 22, 2021
Priority date	Mar 20, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A stacked high-blocking III-V semiconductor power diode and manufacturing method, wherein the III-V semiconductor power diode comprises a first highly doped semiconductor contact area, a low-doped semiconductor drift region disposed beneath the first semiconductor contact area, a highly doped second semiconductor contact area disposed beneath the semiconductor drift region, and two terminal contact layers, at least the first semiconductor contact area forms a core stack, the core stack is surrounded by a dielectric frame region along the side face, the upper surface or lower surface of the core stack and the dielectric frame region terminate with each other or form a step with respect to each other, and semiconductor areas of the III-V semiconductor power diode arranged beneath the first semiconductor contact area are each either surrounded by the core stack or form a carrier portion.

First claim

What is claimed is:

1 . A high-blocking 111-V semiconductor power diode comprising:
a highly doped first semiconductor contact area of a first conductivity type having a dopant concentration of at least 1·10 18 cm- 3 and having a first lattice constant; a low-doped semiconductor drift region of the first conductivity type or of a second conductivity type arranged beneath the first semiconductor contact area having a dopant concentration of 8·10 11 -1·10 15 cm- 3 and having the first lattice constant and a layer thickness of 10 μm-200 μm; a highly doped second semiconductor contact area of the second conductivity type arranged beneath the semiconductor drift region having a dopant concentration of at least 5·10 17 cm- 3 and having a second lattice constant; a highly doped metamorphic buffer layer sequence disposed between the semiconductor drift region and the second semiconductor contact area, the metamorphic buffer layer sequence having the first lattice constant on an upper surface facing the semiconductor drift region and the second lattice constant on a lower surface facing the second semiconductor contact area; a first metallic terminal contact layer, which is formed at least in regions and is materially bonded with an upper surface of the first semiconductor contact area; and a second metallic terminal contact layer, which is formed at least in regions and is arranged beneath a lower surface of the second semiconductor contact area, wherein at least the first semiconductor contact area forms a core stack having an upper surface, a lower surface, and a side face extending from the upper surface to the lower surface, wherein the 111-V semiconductor power diode has a dielectric frame region enclosing the core stack along the side face, the dielectric frame region having an upper surface at an uppermost portion of the dielectric frame region and a lower surface at a lowermost portion of the dielectric frame region, and the upper surface of the dielectric frame region being directly over the lower surface of the dielectric frame region, wherein the upper surface of the core stack terminates with the upper surface of the dielectric frame region or forms a first step to the upper surface of the dielectric frame region, wherein the lower surface of the core stack terminates with the lower surface of the dielectric frame region or forms a second step to the lower surface of the dielectric frame region, and wherein semiconductor areas of the 111-V semiconductor power diode arranged beneath the first semiconductor contact area are each either included in the core stack or form a carrier portion, and wherein the carrier portion is arranged beneath the core stack and the dielectric frame region and is provided with a common lower surface, which is formed by the lower surface of the dielectric frame region and the lower surface of the core stack, and are materially bonded.

2 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the dielectric frame region consists of SixOy or of SixNy or of AlxOy or of TaxOy or of TixOy or of HfxOy or comprises SixOy or SixNy or AlxOy or TaxOy or TixOy or HfxOy.

3 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the 111-V semiconductor power diode has, between the first semiconductor contact area and the semiconductor drift region, a semiconductor interlayer of the first conductivity type having a dopant concentration of 8·10 12 -1·10 16 cm- 3 .

4 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the 111-V semiconductor power diode comprises, between the second semiconductor contact area and the semiconductor drift region, a semiconductor interlayer of the second conductivity type having a dopant concentration of 8·10 12 -1·101s cm-3.

5 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the metamorphic buffer layer sequence has a dopant concentration greater than 5·10 17 cm- 3 and a layer thickness greater than 0.5 μm and less than 20 μm, and is of the first conductivity type or the second conductivity type.

6 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the metamorphic buffer layer sequence is part of the core stack and/or part of the carrier portion.

7 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the 111-V semiconductor power diode comprises a substrate layer, and wherein the substrate layer is formed as part of the carrier portion.

8 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the semiconductor drift region and/or the first semiconductor contact area and/or the second semiconductor contact area consists of GaAs or InGaAs or the semiconductor drift region and/or the first semiconductor contact area and/or the second semiconductor contact area comprise GaAs or InGaAs.

9 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the first conductivity type is p and the second conductivity type is n, or wherein the first conductivity type is n and the second conductivity type is p.

10 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the first semiconductor contact area and/or the second semiconductor contact area is well-shaped.

11 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein the frame region is materially bonded to the side face of the core stack.

12 . The high-blocking 111-V semiconductor power diode according to claim 1 , wherein a cross-section of the core stack has a round circumference or an octagonal circumference.

13 . A high-blocking 111-V semiconductor power diode comprising:
a highly doped first semiconductor contact area of a first conductivity type; a low-doped semiconductor drift region of the first conductivity type or of a second conductivity type arranged beneath the first semiconductor contact area, the semiconductor drift region having a first lattice constant; a highly doped second semiconductor contact area of the second conductivity type arranged beneath the semiconductor drift region, the second semiconductor contact area having a second lattice constant; a highly doped metamorphic buffer layer sequence disposed between the semiconductor drift region and the second semiconductor contact area, the metamorphic buffer layer sequence having the first lattice constant on an upper surface facing the semiconductor drift region and the second lattice constant on a lower surface facing the second semiconductor contact area; a first metallic terminal contact layer materially bonded with an upper surface of the first semiconductor contact area; and a second metallic terminal contact layer arranged beneath a lower surface of the second semiconductor contact area, wherein at least the first semiconductor contact area and the semiconductor drift region form a core stack having an upper surface, a lower surface, and a side face extending from the upper surface to the lower surface, wherein the 111-V semiconductor power diode has a dielectric frame region enclosing the core stack along the side face, the dielectric frame region having an upper surface at an uppermost portion of the dielectric frame region and a lower surface at a lowermost portion of the dielectric frame region, and the upper surface of the dielectric frame region being directly over the lower surface of the dielectric frame region, wherein the upper surface of the core stack terminates with the upper surface of the dielectric frame region, wherein the lower surface of the core st

Assignees

• Azur Space Solar Power Gmbh

Inventors

• Wierzkowski Thorsten
• Fuhrmann Daniel

Classifications

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D62/60

  Impurity distributions or concentrations · CPC title

• H10D8/043

  of planar diodes · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title