Network systems and methods for word based arbitration of data

Patent metadata

Field	Value
Publication number	US-12463741-B2
Application number	US-202117531356-A
Country	US
Kind code	B2
Filing date	Nov 19, 2021
Priority date	Nov 19, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An electronic network system includes a first transmitter circuit that transmits first bits, a second transmitter circuit that transmits second bits, and a port select circuit. The port select circuit includes a first buffer circuit that stores first words in a first packet of the first bits received from the first transmitter circuit, a second buffer circuit that stores second words in a second packet of the second bits received from the second transmitter circuit, and a multiplexer circuit that receives the first words from the first buffer circuit and the second words from the second buffer circuit. The multiplexer circuit interleaves the second words with the first words in an output signal such that a first one of the second words is provided in the output signal after a first one of the first words and before a second one of the first words.

First claim

What is claimed is:

1 . An electronic network system comprising:
a first transmitter circuit that transmits first bits; a second transmitter circuit that transmits second bits; and a port select circuit comprising a first buffer circuit that stores first words in a first packet of the first bits received from the first transmitter circuit, a second buffer circuit that stores second words in a second packet of the second bits received from the second transmitter circuit, and a multiplexer circuit that receives the first words from the first buffer circuit and the second words from the second buffer circuit, wherein the multiplexer circuit interleaves the second words with the first words in a first output signal such that a first one of the second words in the second packet is provided in the first output signal after a first one of the first words in the first packet and before a second one of the first words in the first packet.

2 . The electronic network system of claim 1 further comprising:
a third transmitter circuit that transmits third bits, wherein the port select circuit further comprises a third buffer circuit that stores third words in a third packet of the third bits received from the third transmitter circuit, wherein the multiplexer circuit receives the third words from the third buffer circuit, and wherein the multiplexer circuit interleaves the first, the second, and the third words in the first output signal such that a first one of the third words in the third packet is provided in the first output signal after the first ones of the first and the second words and before the second one of the first words and a second one of the second words in the second packet.

3 . The electronic network system of claim 2 further comprising:
a fourth transmitter circuit that transmits fourth bits, wherein the port select circuit further comprises a fourth buffer circuit that stores fourth words in a fourth packet of the fourth bits received from the fourth transmitter circuit, wherein the multiplexer circuit receives the fourth words from the fourth buffer circuit, and wherein the multiplexer circuit interleaves the first, the second, the third, and the fourth words in the first output signal in response to a clock signal such that one of the fourth words is provided in the first output signal after the first ones of the first, the second, and the third words and before the second ones of the first and the second words and a second one of the third words in the third packet.

4 . The electronic network system of claim 1 further comprising:
a security controller circuit that performs a security function on the first output signal to generate a second output signal indicating the first and the second words; and
a port deselect circuit comprising first and second port circuits and a demultiplexer circuit that receives the second output signal, wherein the demultiplexer circuit provides each of the first words to the first port circuit and each of the second words to the second port circuit.

5 . The electronic network system of claim 2 further comprising:
a port deselect circuit comprising a fourth buffer circuit, a fifth buffer circuit, a sixth buffer circuit, and a demultiplexer circuit that receives the first, the second, and the third words, wherein the demultiplexer circuit provides each of the first words to the fourth buffer circuit to regenerate the first packet, each of the second words to the fifth buffer circuit to regenerate the second packet, and each of the third words to the sixth buffer circuit to regenerate the third packet.

6 . The electronic network system of claim 3 further comprising:
a port deselect circuit comprising a fifth buffer circuit, a sixth buffer circuit, a seventh buffer circuit, an eighth buffer circuit, and a demultiplexer circuit that receives the first, the second, the third, and the fourth words, wherein the demultiplexer circuit provides each of the first words to the fifth buffer circuit to regenerate the first packet, each of the second words to the sixth buffer circuit to regenerate the second packet, each of the third words to the seventh buffer circuit to regenerate the third packet, and each of the fourth words to the eighth buffer circuit to regenerate the fourth packet.

7 . The electronic network system of claim 1 , wherein the port select circuit further comprises a first accumulator circuit that accumulates the first bits received from the first transmitter circuit into the first words and that provides the first words to the first buffer circuit, and wherein the port select circuit further comprises a second accumulator circuit that accumulates the second bits received from the second transmitter circuit into the second words and that provides the second words to the second buffer circuit.

8 . The electronic network system of claim 1 , wherein the first transmitter circuit is dynamically reconfigured to change a transmission speed of the first bits from a first bit rate to a second bit rate that is different than the first bit rate, wherein the second transmitter circuit is dynamically reconfigured to change a transmission speed of the second bits from the first bit rate to the second bit rate, wherein the first buffer circuit stores the first words at each of the first bit rate and the second bit rate, wherein the second buffer circuit stores the second words at each of the first bit rate and the second bit rate, and wherein the multiplexer circuit interleaves the second words with the first words at each of the first bit rate and the second bit rate.

9 . An electronic network system comprising:
a port deselect circuit comprising first and second buffer circuits and a demultiplexer circuit that receives first words of first bits from a first packet that are interleaved with second words of second bits from a second packet such that a first one of the second words is received after a first one of the first words in the first packet and before a second one of the first words in the first packet, wherein the demultiplexer circuit provides each of the first words to the first buffer circuit to regenerate the first packet, and wherein the demultiplexer circuit provides each of the second words to the second buffer circuit to regenerate the second packet.

10 . The electronic network system of claim 9 , wherein the port deselect circuit further comprises first and second downsizer circuits, wherein the first downsizer circuit separates the first bits in each of the first words received from the first buffer circuit to generate first groups of bits, wherein each of the first groups has less bits than each of the first words, wherein the second downsizer circuit separates the second bits in each of the second words received from the second buffer circuit to generate second groups of bits, and wherein each of the second groups has less bits than each of the second words.

11 . The electronic network system of claim 9 further comprising:
a network controller circuit comprising first and second receiver circuits, wherein the port deselect circuit provides the first words to the first receiver circuit, and wherein the port deselect circuit provides the second words to the second receiver circuit.

12 . The electronic network system of claim 9 , wherein the port deselect circuit further comprises a third buffer circuit, wherein the demultiplexer circuit receives third words of third bits that are interleaved with the first and the second words, and wherein the demultiplexer circuit provides each of the third words to the third buffer circuit to regenerate a third packet comprising the third words.

1

Assignees

• Intel Corp
• Altera Corp

Inventors

• Soo Choon Yip

Classifications

• H04L1/0071

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04L49/351

  for local area network [LAN], e.g. Ethernet switches · CPC title

• H04L49/9057

  Arrangements for supporting packet reassembly or resequencing · CPC title

• H04L63/0435

  wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for symmetric key encryption H04L9/06) · CPC title

• H04L63/0471

  applying encryption by an intermediary, e.g. receiving clear information at the intermediary and encrypting the received information at the intermediary before forwarding · CPC title