Dynamic amplifier with reduced sensitivity

Patent metadata

Field	Value
Publication number	US-12463609-B2
Application number	US-202217821115-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.

First claim

The invention claimed is:

1 . A dynamic amplifier comprising:
a pair of differential input nodes comprising a first input node and a second input node; a pair of differential output nodes comprising a first output node and a second output node; a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node; a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node; a first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; and a sixth switch coupled between the second intermediate node and the first output node, wherein:
for a first phase, the first switch, the second switch, the third switch, and the fourth switch are configured to be closed and the fifth switch and the sixth switch are configured to be open; and
for a second phase subsequent to the first phase, the first switch and the second switch are configured to be open and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.

2 . The dynamic amplifier of claim 1 , wherein:
a control input of the first switch is coupled to a control input of the second switch; a control input of the third switch is coupled to a control input of the fourth switch; and a control input of the fifth switch is coupled to a control input of the sixth switch.

3 . The dynamic amplifier of claim 1 , wherein:
a source of the first differential input transistor is coupled to a source of the second differential input transistor at a common-source node; and a voltage of the common-source node is configured to rise during the first phase.

4 . The dynamic amplifier of claim 3 , wherein:
a cross-coupling of the first switch and the second switch compared to the third switch and the fourth switch is configured to allow the voltage of the common-source node to rise during the first phase without a change in a differential output voltage across the pair of differential output nodes; and amplification of a differential input signal across the pair of differential input nodes is configured to occur during the second phase.

5 . The dynamic amplifier of claim 1 , wherein for a third phase subsequent to the second phase, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be open.

6 . The dynamic amplifier of claim 1 , wherein:
the first switch and the second switch are implemented by a first pair of transistors; the third switch and the fourth switch are implemented by a second pair of transistors; and the first pair of transistors has a same transistor size as the second pair of transistors.

7 . A dynamic amplifier comprising:
a pair of differential input nodes comprising a first input node and a second input node; a pair of differential output nodes comprising a first output node and a second output node; a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node; a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node; a first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; a sixth switch coupled between the second intermediate node and the first output node; a seventh switch coupled between the second output node and a power supply rail; an eighth switch coupled between the first output node and the power supply rail, wherein a control input of the seventh switch is coupled to a control input of the eighth switch; and a current sink coupled between a source of the first differential input transistor and a reference potential node, wherein the source of the first differential input transistor is coupled to a source of the second differential input transistor.

8 . The dynamic amplifier of claim 7 , wherein:
for a first phase, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be open; for a second phase subsequent to the first phase, the first switch, the second switch, the third switch, and the fourth switch are configured to be closed and the fifth switch and the sixth switch are configured to be open; and for a third phase subsequent to the second phase, the first switch and the second switch are configured to be open and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.

9 . The dynamic amplifier of claim 8 , wherein:
for the first phase, the seventh switch and the eighth switch are configured to be closed; for the second phase, the seventh switch and the eighth switch are configured to be closed; and for the third phase, the seventh switch and the eighth switch are configured to be open.

10 . An analog-to-digital converter (ADC) comprising the dynamic amplifier of claim 1 , the ADC further comprising a conversion stage configured to generate a digital output and a residue voltage, wherein the dynamic amplifier is coupled to the conversion stage and is configured to amplify the residue voltage.

11 . A method of amplifying with a dynamic amplifier comprising:
a pair of differential input nodes comprising a first input node and a second input node; a pair of differential output nodes comprising a first output node and a second output node; a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node; a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node; a first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; and a sixth switch coupled between the second intermediate node and the first output node, the method comprising:
charging a common-source node of the first differential input transistor and the second differential input transistor during a first phase, the charging including closing the first switch, the second switch, the third switch, and the fourth switch, wherein the fifth switch and the sixth switch are open; and
amplifying a voltage difference between a first input signal at the first input node and a second input signal at the second input node, during a second phase subsequent to the first phase, the amplifying including opening the first switch and the second switch and closing the fifth switch an

Assignees

• Qualcomm Inc

Inventors

• Sedighi Behnam

Classifications

• H03M1/122

  Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45631

  the LC comprising one or more capacitors, e.g. coupling capacitors · CPC title

• H03F2203/45644

  the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors · CPC title

• H03F2203/45396

  the AAC comprising one or more switches · CPC title