Doherty power amplifier

Patent metadata

Field	Value
Publication number	US-12463595-B2
Application number	US-202318163575-A
Country	US
Kind code	B2
Filing date	Feb 2, 2023
Priority date	Mar 10, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Disclosed is an amplifier having a carrier amplifier configured as a common-emitter carrier power stage and a peaking amplifier configured as a common-emitter peaking power stage. Further included is power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

First claim

What is claimed is:

1 . An amplifier comprising:
a carrier amplifier having a common-emitter carrier power stage; a peaking amplifier having a common-emitter peaking power stage; and power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

2 . The amplifier of claim 1 wherein the common-emitter carrier power stage comprises:
a first carrier power transistor having a first carrier emitter coupled to a fixed voltage node, a first carrier base, and a first carrier collector, and a second carrier emitter coupled to the fixed voltage node, a second carrier base, and a second carrier collector; and
a first peaking power transistor having a first peaking emitter coupled to the fixed voltage node, a first peaking base, and a first peaking collector.

3 . The amplifier of claim 2 wherein the power adaptive biasing circuitry comprises:
power adaptive biasing positive (PABP) circuitry coupled between the first carrier base and the first peaking base, wherein the PABP circuitry is configured to sense one of the direct current base voltages that is a direct current base voltage of the first carrier power transistor and in response to generate one of the control currents that debiases the first peaking power transistor; and
power adaptive biasing negative (PABN) circuitry coupled between the second carrier base and the second peaking base, wherein the PABN circuitry is configured to sense one of the direct current base voltages that is a direct current base voltage of the second carrier power transistor and in response to generate one of the control currents that debiases the second peaking power transistor.

4 . The amplifier of claim 3 wherein the PABP circuitry comprises:
a sensor transistor having a sensor emitter coupled to the fixed voltage node, a sensor base, and a sensor collector;
a sense resistor coupled between the first carrier base and the sensor base; and
an isolation resistor coupled between the sensor collector and the first peaking base.

5 . The amplifier of claim 4 wherein the PABP circuitry further comprises a filter capacitor coupled between the sensor base and the fixed voltage node.

6 . The amplifier of claim 3 wherein the PABN circuitry comprises:
a sensor transistor having a sensor emitter coupled to the fixed voltage node, a sensor base, and a sensor collector;
a sense resistor coupled between the second carrier base and the sensor base; and
an isolation resistor coupled between the sensor collector and the second peaking base.

7 . The amplifier of claim 6 wherein the PABN circuitry further comprises a filter capacitor coupled between the sensor base and the fixed voltage node.

8 . The amplifier of claim 3 wherein the PABP circuitry comprises:
a reference transistor having a reference emitter coupled to the fixed voltage node, a reference base, and a reference collector coupled to the reference base;
a mirror transistor having a mirror emitter coupled to the fixed voltage node, a mirror base coupled to the reference base, and a mirror collector;
a sense resistor coupled between the first carrier base and the reference collector; and
an isolation resistor coupled between the mirror collector and the first peaking base.

9 . The amplifier of claim 8 wherein the PABP circuitry further comprises a filter capacitor coupled between the reference collector and the fixed voltage node.

10 . The amplifier of claim 3 wherein the PABN circuitry comprises:
a reference transistor having a reference emitter coupled to the fixed voltage node, a reference base, and a reference collector coupled to the reference base;
a mirror transistor having a mirror emitter coupled to the fixed voltage node, a mirror base coupled to the reference base, and a mirror collector;
a sense resistor coupled between the second carrier base and the reference collector; and
an isolation resistor coupled between the mirror collector and the second peaking base.

11 . The amplifier of claim 8 wherein the PABN circuitry further comprises a filter capacitor coupled between the reference collector and the fixed voltage node.

12 . The amplifier of claim 1 wherein the fixed voltage node is ground.

13 . A method for amplifying a signal, using an amplifier comprising a carrier amplifier having a common-emitter carrier power stage, a peaking amplifier having a common-emitter peaking power stage, and power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, the method comprising:
sensing direct current base voltages of the common-emitter carrier power stage; and generating control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

14 . The method of claim 13 wherein the power adaptive biasing circuitry comprises power adaptive biasing positive (PABP) circuitry coupled between a first carrier base and a first peaking base and power adaptive biasing negative (PABN) circuitry coupled between a second carrier base and a second peaking base, the method further comprising:
sensing one of the direct current base voltages that is a direct current base voltage of a first carrier power transistor;
generating one of the control currents that debiases a first peaking power transistor in response to a sensed direct current base voltage of the first carrier power transistor;
sensing another one of the direct current base voltages that is a direct current base voltage of a second carrier power transistor; and
generating another one of the control currents that debiases a second peaking power transistor in response to a sensed direct current base voltage of the second carrier power transistor.

15 . The method of claim 13 wherein the fixed voltage node is ground.

16 . A wireless communication device comprising:
a baseband processor; transmit circuitry configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data, wherein the transmit circuitry comprises:
a carrier amplifier having a common-emitter carrier power stage;
a peaking amplifier having a common-emitter peaking power stage;
power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage; and
at least one antenna coupled to the transmit circuitry to transmit the carrier signal.

17 . The wireless communications device of claim 16 wherein the common-emitter carrier power stage comprises:
a first carrier power transistor having a first carrier emitter coupled to a fixed voltage node, a first carrier base, and a first carrier collector, and a second carrier emitter coupled to the fixed voltage node, a second carrier base, and a second carrier collector; and
a first peaking power transistor having a first peaking emitter coupled to the fixed voltage node, a first peaking base, and a first peaking collector.

Assignees

• Qorvo Us Inc

Inventors

• Ji Ming
• Teeter Douglas Andrew

Classifications

• H04B1/04

  Circuits · CPC title

• H03F2203/21127

  the input bias current of a power amplifier being controlled, e.g. by an active current source or a current mirror · CPC title

• H03F2200/481

  A resistor being used as sensor · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/267

  A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit · CPC title