Microdevice cartridge structure

Patent metadata

Field	Value
Publication number	US-12463162-B2
Application number	US-201917293441-A
Country	US
Kind code	B2
Filing date	Nov 18, 2019
Priority date	Nov 16, 2018
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

What is disclosed is structures and methods of integrating micro devices into system substrate. Further, the disclosure, also relates to methods and structures for enhancing the bonding process of micro-devices into a substrate. More specifically, it relates to expanding the micro device area or bonding area of micro devices.

First claim

The invention claimed is:

1 . A micro device structure that comprises of:
i. a top and bottom doped layer, ii. active or functional layers, comprising multi quantum wells, barrier, blocking, and cladding, between the top and bottom layers, iii. a VIA from the top doped layer to the bottom doped layer where the VIA is passivated with a dielectric and filled partially or fully by a conductive material that passes a contact from the top doped layer to the bottom doped layer; and iv. a top surface of the micro device structure is covered by a dielectric layer.

2 . The micro device structure of claim 1 , further comprising a first pad or bump formed on the top surface of the micro device structure with openings in the dielectric layer to provide access to a conductive layer.

3 . The micro device structure of claim 1 , further comprising an ohmic layer partially or fully coupled to the top or the bottom doped layer.

4 . The micro device structure of claim 1 , further comprising a sacrificial layer formed on the top of the microdevice structure.

5 . The micro device structure of claim 4 , wherein the sacrificial layer is patterned to have one or more openings to the micro device structure for forming an anchor.

6 . The micro device structure of claim 5 , wherein an area on top of a protective layer formed on the micro device structure has an opening in the sacrificial layer.

7 . The micro device structure of claim 4 , wherein the micro device structure is formed on a first micro device substrate and further comprises a planarization layer formed on the sacrificial layer, the planarization layer surrounding the micro device structure.

8 . The micro device structure of claim 7 , wherein an opening in the sacrificial layer is filled with the planarization layer forming an anchor.

9 . The micro device structure of claim 7 , wherein a bonding layer for bonding the micro device structure onto a secondary substrate is formed on the planarization layer.

10 . The micro device structure of claim 9 , the planarization layer is developed and cured before bonding with a bonding layer.

11 . The micro device structure of claim 9 , the first micro device substrate is separated from the micro device structure leaving the micro device structure bonded to the secondary substrate.

12 . The micro device structure of claim 11 , wherein an etch back can expose the surface of the planarization layer.

13 . The micro device structure of claim 12 , wherein a bottom of the VIA is etched back to provide access to the conductive material.

14 . The micro device structure of claim 11 , wherein a layer formed on the bottom to connect the conductive layer to a bottom surface.

15 . The micro device structure of claim 1 , wherein a second pad or bump is formed on the top surface of the micro device structure to connect to a top ohmic or the top doped layer.

16 . A micro device structure that comprises of:
a top and bottom doped layer, active or functional layers, comprising multi quantum wells, barrier, blocking, and cladding, between the top and bottom layers, a VIA from the top doped layer to the bottom doped layer where the VIA is passivated with a dielectric and filled partially or fully by a conductive material that passes a contact from the top doped layer to the bottom doped layer; and the VIA is coupled to the top doped layer through extension of a conductive layer on top of the VIA.

17 . The micro device structure of claim 16 , where there is an ohmic layer partially or fully coupled to the top or bottom doped layer.

18 . The micro device structure of claim 16 , where a pad or bump is formed coupled with the conductive material while separated from the bottom ohmic or doped layer by a dielectric.

19 . The micro device structure of claim 16 , where another bump or pad is formed to couple with the bottom ohmic or doped layer.

20 . The micro device structure of claim 16 , where a protective layer is formed on the top of the microdevice covering the VIA.

Assignees

• Vuereal Inc

Inventors

• Chaji Gholamreza
• Fathi Ehsanollah

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title