Semiconductor memory including a current comparison readout circuit

Patent metadata

Field	Value
Publication number	US-12462882-B2
Application number	US-202117928333-A
Country	US
Kind code	B2
Filing date	Apr 27, 2021
Priority date	Nov 30, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.

First claim

What is claimed is:

1 . A semiconductor memory, comprising:
a first memory array including a plurality of memory cells; a second memory array including a plurality of memory cells; a comparison readout circuit including a first port and a second port, the first port being configured to receive an electrical signal of a read memory cell, the second port being configured to receive a reference electrical signal, the comparison readout circuit being configured to compare the electrical signal of the read memory cell with the reference electrical signal, so as to obtain storage information of the read memory cell; a first column decoder coupled to the first memory array and the comparison readout circuit, configured to select a bitline (BL) corresponding to the read memory cell when a memory array selection signal enables the first memory array, and output the electrical signal of the memory cell to the first port through the BL, and further configured to couple a first BL of the first memory array to the second port when the memory array selection signal does not enable the first memory array; and a second column decoder coupled to the second memory array and the comparison readout circuit, configured to select a BL corresponding to the read memory cell when the memory array selection signal enables the second memory array, and output the electrical signal of the memory cell to the first port through the BL, and further configured to couple a second BL of the second memory array to the second port when the memory array selection signal does not enable the second memory array wherein the first column decoder and the second column decoder each include an A×B two-level decoder, each two-level decoder includes B first selection switches and A second selection switches, an input terminal of each second selection switch is coupled to a BL, each second selection switch is configured to turn on the coupled BL when enabled, each address decoder controls each second selection switch through A second-level switch signals, and each second-level switch signal controls turn-on of B consecutive address BLs; an input terminal of each first selection switch is coupled to output terminals of the A second selection switches, an output terminal of each first selection switch is coupled to the first port, and each address decoder controls turn-on of the B first selection switches through B first-level switch signals in a one-to-one corresponding manner; and each of the first selection switches is controlled by column selection address low-order decoding output, and each of the second selection switches is controlled by column selection address high-order decoding output.

2 . The semiconductor memory according to claim 1 , wherein when the first memory array is enabled, the second memory array is in a disabled state, and when the second memory array is enabled, the first memory array is in the disabled state.

3 . The semiconductor memory according to claim 1 , wherein the first column decoder and the second column decoder each include an address decoder including:
an address input terminal configured to input an address of the read memory cell; a memory array selection signal input terminal configured to input the memory array selection signal; an operating voltage input terminal configured to input an operating voltage; a column selection address low-order decoding terminal coupled to each of the first selection switches and configured to output a column selection address low-order decoding output signal; and a column selection address high-order decoding terminal coupled to each of the second selection switches and configured to output a column selection address high-order decoding output signal.

4 . The semiconductor memory according to claim 3 , wherein in a standby mode and when the memory array selection signal does not enable the first memory array, the memory array selection signal input by the memory array selection signal input terminal of the first column decoder is 0, and the column selection address low-order decoding terminal and the column selection address high-order decoding terminal of the first column decoder output corresponding high-level signals as the first-level switch signal and the second-level switch signal to control the first selection switch and the second selection switch corresponding to the first BL to be turned on, so as to couple the first BL of the first memory array to the second port; and
wherein in the standby mode and when the memory array selection signal does not enable the second memory array, the memory array selection signal input by the memory array selection signal input terminal of the second column decoder is 0, and the column selection address low-order decoding terminal and the column selection address high-order decoding terminal of the second column decoder output corresponding high-level signals as the first-level switch signal and the second-level switch signal to control the first selection switch and the second selection switch corresponding to the second BL to be turned on, so as to couple the second BL of the second memory array to the second port.

5 . The semiconductor memory according to claim 3 , wherein the operating voltage is 2.5 V.

6 . The semiconductor memory according to claim 5 , wherein the semiconductor memory further includes a charge pump, and the operating voltage is supplied by the charge pump.

7 . The semiconductor memory according to claim 6 , wherein the high-level signals output by the column selection address low-order decoding terminal and the column selection address high-order decoding terminal of each address decoder are 2.5 V signals supplied by the charge pump.

8 . The semiconductor memory according to claim 1 , wherein the comparison readout circuit is a current comparison readout circuit, the electrical signal of the read memory cell is an on current of the memory cell, and the reference electrical signal is a reference current.

9 . The semiconductor memory according to claim 8 , further comprising a bandgap reference coupled to the second port and configured to generate the reference current.

10 . The semiconductor memory according to claim 8 , wherein when the memory cell stores data “1”, the on current is greater than the reference current, and the current comparison readout circuit outputs “1”, and wherein when the memory cell stores data “0”, the on current is less than the reference current, and the current comparison readout circuit outputs “0”.

11 . The semiconductor memory according to claim 1 , wherein each of the memory cells includes four ports: a word line, a BL, a source line, and a substrate.

12 . The semiconductor memory according to claim 1 , wherein the semiconductor memory is a flash memory.

13 . The semiconductor memory according to claim 12 , wherein the semiconductor memory is an embedded flash memory.

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Gu Ming
• Wang Hao
• Guo Shuming
• Li Youhui
• Chen Bin
• Hu Yongqiang

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title