In-memory computation device having improved drift compensation

Patent metadata

Field	Value
Publication number	US-12462858-B2
Application number	US-202318542938-A
Country	US
Kind code	B2
Filing date	Dec 18, 2023
Priority date	Dec 23, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An in-memory computation device includes a word line activation circuit that receives an input signal indicative of input values and provides activation signals each as a function of the input value. The in-memory computation device further includes a memory array, a biasing circuit generating a bias voltage and a digital detector. The memory array has memory cells coupled to a bit line and each to a word line. Each memory cell stores a computational weight. In response to an activation signal, a cell current flows through each memory cell as a function of the bias voltage, the activation signal and the computational weight. A bit line current flows through the bit line as a function of a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides an output signal.

First claim

The invention claimed is:

1 . An in-memory computation device, comprising:
a word line activation circuit configured to receive an input signal indicative of a plurality of input values and to provide a plurality of activation signals, wherein each activation signal is a function of a respective input value; a biasing circuit configured to provide a bias voltage in response to a reference current; a memory array comprising a plurality of memory cells coupled to a bit line and coupled each to a respective word line, wherein the bit line is configured to receive the bias voltage, wherein the memory cells are configured to each store a respective computational weight and to each receive a respective activation signal from the respective word line, wherein a respective cell current flows through each memory cell as a function of the bias voltage, the respective activation signal and the respective computational weight, and wherein a bit line current flows through the bit line as a function of a summation of the cell currents; and a digital detector coupled to the bit line and configured to sample the bit line current and, in response, provide at least one output signal.

2 . The in-memory computation device according to claim 1 , wherein the biasing circuit comprises a reference network having a variable reference impedance through which the reference current flows, wherein the bias voltage is a function of the reference current and the variable reference impedance.

3 . The in-memory computation device according to claim 2 , wherein the reference network comprises a reference memory array configured to have a reference transconductance value, wherein the variable reference impedance is a function of the reference transconductance value, the reference memory array representing a statistically significant sample of the memory array.

4 . The in-memory computation device according to claim 1 , wherein the activation signals are each a pulse signal having a duration that is a proportional function of the respective input value.

5 . The in-memory computation device according to claim 1 , wherein the word line activation circuit comprises a timer configured to provide a timer signal, and a plurality of input-time converters configured to compare the timer signal with a respective input value and, in response, to provide the respective activation signal.

6 . The in-memory computation device according to claim 5 , wherein the timer is configured to provide the timer signal in response to an oscillator current, wherein the timer is configured to update the timer signal at an update frequency that is a function of the oscillator current.

7 . The in-memory computation device according to claim 6 , wherein the timer is configured to generate the oscillator current from the reference current.

8 . The in-memory computation device according to claim 7 , further configured to receive an external signal from a user, wherein the oscillator current is a function of the external signal.

9 . The in-memory computation device according to claim 8 , wherein the timer comprises an integration stage and a counter stage and is configured to perform a number of successive timing iterations, wherein, in each timing iteration:
the integration stage is configured to generate a respective integration signal indicative of a time integral of the oscillator current, compare the integration signal with an oscillator threshold, and reset the integration signal in response to the integration signal reaching the oscillator threshold; and the counter stage is configured to update the timer signal in response to the integration signal reaching the oscillator threshold.

10 . The in-memory computation device according to claim 5 , wherein the word line activation circuit is configured to compare the timer signal with a maximum count signal and, in response, to provide an end-computation signal, wherein the digital detector is configured to receive the end-computation signal and stop sampling the bit line current in response to receiving the end-computation signal.

11 . The in-memory computation device according to claim 1 , wherein the digital detector comprises an integration stage and a counter stage, and is configured to perform a number of successive sampling iterations, wherein, in each sampling iteration:
the integration stage is configured to generate an integration signal indicative of a time integral of the bit line current, compare the integration signal with a sampling threshold, and reset the integration signal in response to the integration signal reaching the sampling threshold; and the counter stage is configured to update the output signal in response to the integration signal reaching the sampling threshold.

12 . The in-memory computation device according to claim 11 , wherein the integration stage of the digital detector has a same circuit diagram as the integration stage of the timer.

13 . The in-memory computation device according to claim 11 , wherein the integration stage comprises a first inverter having an output providing the integration signal, and an integration capacitive element coupled at the output of the first inverter, wherein the first inverter is configured to receive a biasing current indicative of the bit line current.

14 . The in-memory computation device according to claim 13 , wherein the first inverter has an input configured to receive a control signal indicative of the integration signal reaching the sampling threshold, and wherein the first inverter is configured, as a function of the control signal, to charge the integration capacitive element with the biasing current or to discharge the integration capacitive element.

15 . The in-memory computation device according to claim 11 , wherein the integration stage comprises a first operational amplifier having a first input and an output, and an integration capacitive element coupled between the first input of the first operational amplifier and the output of the first operational amplifier, and wherein the first operational amplifier is configured to receive, at the first input, a current indicative of the bit line current.

16 . The in-memory computation device according to claim 11 , wherein the integration stage comprises a second inverter having a switching threshold and receiving the integration signal, wherein the sampling threshold is the switching threshold of the second inverter.

17 . The in-memory computation device according to claim 11 , wherein the integration stage comprises a second operational amplifier having a first input and a second input, and wherein the second operational amplifier is configured to receive the integration signal at the first input and the sampling threshold at the second input.

18 . The in-memory computation device according to claim 11 , wherein the integration signal is a first integration signal and the sampling threshold is a first sampling threshold, the integration stage comprising a first integration circuit configured to generate the first integration signal, compare the first integration signal with the first sampling threshold and reset the first integration signal, the integration stage further comprising a second integration circuit and a switching circuit coupled between the first and the second integration circuits;
wherein the second integration circuit is configured to generate a second integration signal indicative of a time integral of the bit line current, compare the second integration signal with a second sampling threshold and r

Assignees

• St Microelectronics Srl

Inventors

• Carissimi Marcella
• Pasotti Marco
• Zurla Riccardo

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G06N3/065

  Analogue means · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title