Gate driver, display device including the same, and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-12462740-B2
Application number	US-202418961378-A
Country	US
Kind code	B2
Filing date	Nov 26, 2024
Priority date	Feb 2, 2024
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A gate driver includes stages, each including a first pull-up control circuit configured to apply a previous carry signal to a first control node, a buffer circuit configured to output a gate clock signal as a gate output signal, and a pull-down circuit configured to output a second low voltage as the gate output signal. The first pull-up control circuit includes a 4-1 st transistor including a control electrode, a first electrode, and a second electrode connected to a second control node. The first pull-up control circuit includes a 4-2 nd transistor including a control electrode, a first electrode connected to the second control node, and a second electrode connected to a first control node. The first pull-up control circuit includes a hold capacitor including a first electrode connected to the second control node and a second electrode configured to receive a constant voltage.

First claim

What is claimed is:

1 . A gate driver comprising a plurality of stages, each stage of the plurality of stages comprising:
a first pull-up control circuit configured to apply a previous carry signal among carry signals of previous stages to a first control node in response to the previous carry signal; a buffer circuit configured to output a gate clock signal as a gate output signal in response to a signal of the first control node; and a pull-down circuit configured to output a second low voltage as the gate output signal in response to a first subsequent carry signal among carry signals of subsequent stages, wherein the first pull-up control circuit comprises:
a 4-1 st transistor comprising a control electrode configured to receive the previous carry signal, a first electrode configured to receive the previous carry signal, and a second electrode connected to a second control node;
a 4-2 nd transistor comprising a control electrode configured to receive the previous carry signal, a first electrode connected to the second control node, and a second electrode connected to the first control node; and
a hold capacitor comprising a first electrode connected to the second control node and a second electrode configured to receive a constant voltage.

2 . The gate driver of claim 1 , wherein the constant voltage is a first low voltage less than the second low voltage.

3 . The gate driver of claim 1 , wherein the constant voltage is the second low voltage.

4 . The gate driver of claim 1 , wherein the constant voltage is a high gate voltage which defines a high level of the gate output signal.

5 . The gate driver of claim 1 , wherein, when the previous carry signal transitions from a first low voltage less than the second low voltage to a high gate voltage which defines a high level of the gate output signal, the high gate voltage is applied to the second control node and the first control node, and
wherein, when the previous carry signal transitions from the high gate voltage to the first low voltage, a signal of the second control node is maintained as the high gate voltage.

6 . The gate driver of claim 5 , wherein the signal of the second control node is maintained as the high gate voltage in a period in which the signal of the first control node is greater than the high gate voltage.

7 . The gate driver of claim 1 , wherein each stage of the plurality of stages further comprises:
an inverter configured to output one of a direct current (DC) inverter voltage and a first low voltage less than the second low voltage to a third control node in response to the DC inverter voltage and the signal of the first control node.

8 . The gate driver of claim 7 , wherein the inverter comprises:
a 12-1 st transistor comprising a control electrode configured to receive the DC inverter voltage, a first electrode configured to receive the DC inverter voltage, and a second electrode connected to a twelfth intermediate node; a 12-2 nd transistor comprising a control electrode configured to receive the DC inverter voltage, a first electrode connected to the twelfth intermediate node, and a second electrode; a seventh transistor comprising a control electrode connected to the second electrode of the 12-2 nd transistor, a first electrode configured to receive the DC inverter voltage, and a second electrode connected to the third control node; a thirteenth transistor comprising a control electrode connected to the first control node, a first electrode connected to the control electrode of the seventh transistor, and a second electrode configured to receive the second low voltage; and an eighth transistor comprising a control electrode connected to the first control node, a first electrode connected to the third control node, and a second electrode configured to receive the first low voltage.

9 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a second pull-up control circuit configured to apply the first low voltage to the first control node in response to a second subsequent carry signal among the carry signals of the subsequent stages.

10 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a first hold circuit configured to apply the first low voltage to the first control node in response to a signal of the third control node.

11 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a second hold circuit configured to output the second low voltage as the gate output signal in response to a signal of the third control node.

12 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a carry buffer circuit configured to output a carry clock signal as a carry signal in response to the signal of the first control node; and a carry pull-down circuit configured to output the first low voltage as the carry signal in response to the first subsequent carry signal.

13 . The gate driver of claim 12 , wherein each stage of the plurality of stages further comprises:
a third hold circuit configured to output the first low voltage as the carry signal in response to a signal of the third control node.

14 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a reset circuit configured to apply the first low voltage to the first control node in response to a reset signal.

15 . The gate driver of claim 7 , wherein each stage of the plurality of stages further comprises:
a sensing selection circuit configured to apply the previous carry signal to a sensing control node in response to a first sensing signal.

16 . The gate driver of claim 15 , wherein each stage of the plurality of stages further comprises:
a first sensing control circuit configured to apply a gate high voltage which defines a high level of the gate output signal to the first control node in response to a signal of the sensing control node and a second sensing signal; and a second sensing control circuit configured to apply the first low voltage to the third control node in response to the signal of the sensing control node and the second sensing signal.

17 . The gate driver of claim 1 , wherein each stage of the plurality of stages further comprises:
a second buffer circuit configured to output a second gate clock signal as a second gate output signal in response to the signal of the first control node; and a second pull-down circuit configured to output the second low voltage as the second gate output signal in response to the first subsequent carry signal.

18 . The gate driver of claim 17 , wherein each stage of the plurality of stages further comprises:
a fourth hold circuit configured to output the second low voltage as the second gate output signal in response to a signal of a third control node.

19 . The gate driver of claim 1 , wherein the buffer circuit comprises:
a first transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the gate clock signal, and a second electrode connected to a gate output terminal; and a first capacitor comprising a first electrode connected to the control electrode of the first transistor and a second electrode connected to the gate output terminal, and wherein the pull-down circuit comprises: a second transistor comprising a control electrode configured to receive the first subsequent carry signal, a first electrode config

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Eok Su

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title