Phase clock performance improvement for a system embedded with GNSS receiver
US-2021266086-A1 · Aug 26, 2021 · US
US12461876B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12461876-B2 |
| Application number | US-202318478152-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2023 |
| Priority date | May 10, 2022 |
| Publication date | Nov 4, 2025 |
| Grant date | Nov 4, 2025 |
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In some implementations, a device may receive, via a universal serial bus (USB) interface, configuration information and a supply of power from a network device. The device may receive, via an antenna that is external to the device, a first signal indicating timing information. The device may generate, based on the first signal, a second signal and a third signal, wherein the second signal comprises a one pulse per second signal and the third signal comprises a ten-megahertz signal. The device may provide, to the network device, the second signal and the third signal. The device may receive, via an input port, a clock signal to provide an extended holdover functionality to the network device.
Opening claim text (preview).
What is claimed is: 1 . A method, comprising: providing, by a first device and via a universal serial bus (USB) interface, configuration information and a supply of power to a second device; obtaining, by the first device and from the second device, a first signal and a second signal, wherein the first signal and the second signal are generated based on a third signal obtained via an antenna, and wherein the first signal comprises a first frequency signal and the second signal comprises a second frequency signal; and providing, by the first device, a fourth signal, wherein the fourth signal comprises a clock signal that enables the second device to perform an extended holdover functionality to the first device. 2 . The method of claim 1 , wherein the configuration information indicates one or more of: a length of a cable connecting a dongle and the first device, a length of a cable connecting a dongle and the antenna, or data associated with modifying a firmware of the first device. 3 . The method of claim 1 , wherein the second device is a global navigation satellite system (GNSS) receiver. 4 . The method of claim 1 , wherein the third signal is a global navigation satellite system (GNSS) signal. 5 . The method of claim 1 , further comprising: obtaining a one pulse per second signal. 6 . The method of claim 1 , wherein the second signal enables the first device to track phase or frequency. 7 . The method of claim 1 , further comprising: performing the extended holdover functionality based on a quality of the third signal. 8 . A first device, comprising: one or more memories; and one or more processors to: provide, via a universal serial bus (USB) interface, configuration information and a supply of power to a second device; obtain, from the second device, a first signal and a second signal, wherein the first signal and the second signal are generated based on a third signal obtained via an antenna, and wherein the first signal comprises a first frequency signal and the second signal comprises a second frequency signal; and provide a fourth signal, wherein the fourth signal comprises a clock signal that enables the second device to perform an extended holdover functionality to the first device. 9 . The first device of claim 8 , wherein the configuration information indicates one or more of: a length of a cable connecting a dongle and the first device, a length of a cable connecting a dongle and the antenna, or data associated with modifying a firmware of the first device. 10 . The first device of claim 8 , wherein the second device is a global navigation satellite system (GNSS) receiver. 11 . The first device of claim 8 , wherein the third signal is a global navigation satellite system (GNSS) signal. 12 . The first device of claim 8 , wherein the one or more processors are further to: obtain a one pulse per second signal. 13 . The first device of claim 8 , wherein the second signal enables the first device to track phase or frequency. 14 . The first device of claim 8 , wherein the one or more processors are further to: perform the extended holdover functionality based on a quality of the third signal. 15 . A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a first device, cause the first device to: provide, via a universal serial bus (USB) interface, configuration information and a supply of power to a second device; obtain, from the second device, a first signal and a second signal, wherein the first signal and the second signal are generated based on a third signal obtained via an antenna, and wherein the first signal comprises a first frequency signal and the second signal comprises a second frequency signal; and provide a fourth signal, wherein the fourth signal comprises a clock signal that enables the second device to perform an extended holdover functionality to the first device. 16 . The non-transitory computer-readable medium of claim 15 , wherein the configuration information indicates one or more of: a length of a cable connecting a dongle and the first device, a length of a cable connecting a dongle and the antenna, or data associated with modifying a firmware of the first device. 17 . The non-transitory computer-readable medium of claim 15 , wherein the second device is a global navigation satellite system (GNSS) receiver. 18 . The non-transitory computer-readable medium of claim 15 , wherein the third signal is a global navigation satellite system (GNSS) signal. 19 . The non-transitory computer-readable medium of claim 15 , wherein the second signal enables the first device to track phase or frequency. 20 . The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions further cause the first device to: perform the extended holdover functionality based on a quality of the third signal.
Universal serial bus [USB] · CPC title
on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title
Tuning or receiving; Circuits therefor · CPC title
Synchronisation (radio-controlled time-pieces G04R) · CPC title
External master-clock · CPC title
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