System on a chip with always-on processor

Patent metadata

Field	Value
Publication number	US-12460950-B2
Application number	US-202117372764-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	May 29, 2014
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory; and a first component coupled to the plurality of components, wherein:
the first component comprises a second memory;
the first component is configured to remain powered on while the plurality of components are powered off;
the first component is configured to capture a plurality of samples of sensor data from at least one sensor in a system that includes the integrated circuit, and the first component is configured to write the plurality of samples to the second memory;
the first component is configured to search the plurality of samples in the second memory for a predetermined pattern;
the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples; and
the first component is configured to transfer the captured plurality of samples from the second memory to the first memory while the CPU processor remains powered off.

2 . The integrated circuit as recited in claim 1 wherein:
the first component is configured to cause the plurality of components to be powered on responsive to the at least one sensor detecting a predetermined event separate from the plurality of samples.

3 . The integrated circuit as recited in claim 2 wherein the predetermined event is a user interaction with a user interface device.

4 . The integrated circuit as recited in claim 1 wherein:
the first component is configured to cause the plurality of components to be powered on in response to a detection of the predetermined pattern; and
the first component is configured to transfer the plurality of samples to the first memory for processing by the CPU processor.

5 . The integrated circuit as recited in claim 4 wherein the first component comprises a first processor configured to cause the power on of the plurality of components.

6 . The integrated circuit as recited in claim 5 wherein the first processor is further configured to search the plurality of samples for the predetermined pattern.

7 . The integrated circuit as recited in claim 6 wherein the first component comprises a power manger circuit configured to power gate the first processor at times other than times in which the first processor is searching the plurality of samples for the predetermined pattern and times in which the first processor is causing the power on of the plurality of components.

8 . The integrated circuit as recited in claim 5 wherein the first component further comprises a sensor capture circuit configured to capture the plurality of samples of sensor data from the sensor and write the plurality of samples to the second memory while the first processor is power gated.

9 . A method comprising:
capturing a plurality of samples of sensor data from at least one sensor in a system that includes an integrated circuit, wherein the integrated circuit comprises a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory, and wherein the integrated circuit comprises a first component coupled to the plurality of components, wherein the first component is configured to remain powered on while the plurality of components are powered off, and wherein the first component comprises a second memory, and wherein the first component is configured to perform the capturing; writing the plurality of samples to the second memory by the first component; searching the plurality of samples in the second memory by the first component for a predetermined pattern; causing the memory controller and a communication path to the memory controller from the first component to be powered on by the first component while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples; and transferring the captured plurality of samples from the second memory to the first memory while the CPU processor remains powered off.

10 . The method as recited in claim 9 further comprising:
causing the plurality of components to be powered on by the first component responsive to the at least one sensor detecting a predetermined event separate from the plurality of samples.

11 . The method as recited in claim 10 wherein the predetermined event is a user interaction with user interface device.

12 . The method as recited in claim 9 further comprising:
causing, by the first component, the plurality of components to be powered on in response to a detection of the predetermined pattern; and
transferring, by the first component, the plurality of samples to the first memory for processing by the CPU processor.

13 . The method as recited in claim 12 wherein the first component further comprises a first processor, and wherein causing the power on of the plurality of components is performed by the first processor.

14 . The method as recited in claim 13 wherein searching the plurality of samples for the predetermined pattern is performed by the first processor.

15 . The method as recited in claim 14 further comprising power gating the first processor at times other than times in which the first processor is searching the plurality of samples for the predetermined pattern and times in which the first processor is causing power on of the plurality of components.

16 . The method as recited in claim 13 wherein the first component further comprises a sensor capture circuit, and wherein capturing the plurality of samples of sensor data from the sensor and writing the plurality of samples to the second memory are performed by the sensor capture circuit while the first processor is power gated.

17 . A system comprising:
at least one sensor; an external memory; and an integrated circuit comprising a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory, and the integrated circuit further comprising a first component coupled to the plurality of components, wherein:
the first component comprises a second memory;
the first component is configured to remain powered on while the plurality of components are powered off;
the first component is configured to capture a plurality of samples of sensor data from the at least one sensor, and the first component is configured to write the plurality of samples to the second memory;
the first component is configured to search the plurality of samples in the second memory for a predetermined pattern;
the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality

Assignees

• Apple Inc

Inventors

• Tripathi Brijesh
• Keil Shane J
• Gulati Manu
• Cho Jung Wook
• Machnicki Erik P
• Herbeck Gilbert H
• Millet Timothy J
• De Cesare Joshua P
• Dalal Anand

Classifications

• B60P1/433

  the loading floor or a part thereof being movable to form the ramp · CPC title

• A61G3/061

  using ramps · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title