Method of forming contact structure, method of fabricating semiconductor device, contact structure and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-12457791-B2
Application number	US-202218148815-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Jan 18, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Disclosed are a method of forming a contact structure, a method of fabricating a semiconductor device, a contact structure, and a semiconductor device including the same. A method of forming a contact structure may comprise forming a porous silicon layer on a substrate by using an epitaxy process, forming a dielectric layer on the porous silicon layer, forming a metal layer on the dielectric layer, forming a silicide member having a three-dimensional structure in the porous silicon layer by diffusing metal atoms of the metal layer into the porous silicon layer through the dielectric layer and reacting the diffused metal atoms with the porous silicon layer in a heat treatment process, removing the metal layer and the dielectric layer, and forming a conductive layer in contact with the silicide member.

First claim

What is claimed is:

1. A method of forming a contact structure, comprising:
forming a porous silicon layer on a substrate by using an epitaxy process;
forming a dielectric layer on the porous silicon layer;
forming a metal layer on the dielectric layer;
forming a silicide member having a three-dimensional structure in the porous silicon layer by diffusing metal atoms of the metal layer into the porous silicon layer through the dielectric layer and reacting the diffused metal atoms with the porous silicon layer in a heat treatment process;
removing the metal layer and the dielectric layer;
etching at least a portion of the porous silicon layer to at least partially expose the three-dimensional structure of the silicide member after removing the metal layer and the dielectric layer; and
forming a conductive layer in contact with the silicide member, wherein the conductive layer is formed to three-dimensionally contact the three-dimensional structure of the exposed silicide member.

2. The method of claim 1 , wherein the porous silicon layer has a porosity of about 10 to about 30 vol %.

3. The method of claim 1 , wherein the porous silicon layer is formed by a plasma enhanced chemical vapor deposition (PECVD) method at a process temperature of room temperature to about 300° C.

4. The method of claim 1 , wherein the dielectric layer has a porosity of less than 5 vol %.

5. The method of claim 1 , wherein the dielectric layer has a thickness of about 0.1 nm to about 200 nm.

6. The method of claim 1 , wherein the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and zirconium oxide.

7. The method of claim 1 , wherein the metal layer includes one or more of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), and molybdenum (Mo).

8. The method of claim 1 , wherein the heat treatment process is performed at a temperature of about 300° C. to about 950° C.

9. The method of claim 1 , wherein the silicide member has a dendrite structure.

10. The method of claim 1 , wherein forming the porous silicon layer includes:
forming a mask layer having an opening on the substrate, the opening exposing a first region of the substrate;
forming a silicon material layer on the first region and the mask layer, wherein the silicon material layer includes a first silicon layer formed on the first region and a second silicon layer formed on the mask layer, and wherein the first silicon layer has a crystalline structure and the second silicon layer has an amorphous structure; and
removing the second silicon layer, and
wherein the first silicon layer formed on the first region corresponds to the porous silicon layer.

11. The method of claim 10 , wherein the first region of the substrate has a crystal plane in a (100) direction.

12. The method of claim 10 , wherein the mask layer is an insulating layer.

13. The method of claim 10 , wherein the second silicon layer is removed by an etching process using hydrogen plasma.

14. A method of fabricating a semiconductor device comprising a contact structure, the method comprising: forming the contact structure by using the method according to claim 1 .

15. A contact structure of a semiconductor device, comprising:
a substrate;
a silicide member disposed on the substrate and having a three-dimensional structure; and
a conductive layer disposed on the substrate to be in contact with the silicide member and disposed to three-dimensionally contact the three-dimensional structure of the silicide member by embedding at least a portion of the silicide member therein; and
a porous silicon layer which is disposed between the substrate and the conductive layer, and has an epitaxial structure,
wherein a lower portion of the silicide member is embedded in the porous silicon layer, and an upper portion of the silicide member is embedded in the conductive layer.

16. The contact structure of a semiconductor device of claim 15 , wherein the silicide member has a dendrite structure.

17. The contact structure of a semiconductor device of claim 15 , wherein the porous silicon layer has a porosity of about 10 to about 30 vol %.

18. The contact structure of a semiconductor device of claim 15 , wherein an upper portion of the substrate has a crystal plane in a (100) direction.

19. A semiconductor device comprising the contact structure according to claim 15 .

Assignees

• Sk Hynix Inc
• Nat Univ Chungbuk Ind Acad Coop Found
• Univ Korea Res & Business Foundation Sejong Campus
• Korea Inst Energy Res

Inventors

• Kim Ka-Hyun
• Lee Hyun Seok
• Lee Jae Woo
• Oh Joon-Ho

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/0113 Primary

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D64/62 Primary

  Electrodes ohmically coupled to a semiconductor · CPC title