Conductive contacts wrapped around epitaxial source or drain regions

Patent metadata

Field	Value
Publication number	US-12457778-B2
Application number	US-202217681263-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Feb 25, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first semiconductor device having a subfin and one or more first semiconductor bodies extending between a first source or drain region and a second source or drain region; a second semiconductor device having the subfin and one or more second semiconductor bodies extending between the first source or drain region and a third source or drain region; a dielectric layer adjacent to the subfin of the first semiconductor device and the second semiconductor device; a conductive layer that extends completely around the first source or drain region between the one or more first semiconductor bodies and the one or more second semiconductor bodies; and a conductive contact extending through a thickness of the dielectric layer and contacting the conductive layer from below the first source or drain region.

2 . The integrated circuit of claim 1 , wherein the one or more first semiconductor bodies comprise one or more nanoribbons, nanowires or nanosheets, and the one or more second semiconductor bodies comprise one or more nanoribbons, nanowires or nanosheets.

3 . The integrated circuit of claim 1 , wherein the conductive contact further contacts a backside conductive layer below the first source or drain region.

4 . The integrated circuit of claim 1 , further comprising a silicide layer directly between the first source or drain region and the conductive layer.

5 . The integrated circuit of claim 1 , wherein the conductive contact extends along a sidewall of at least a portion of the subfin below the first source or drain region.

6 . The integrated circuit of claim 1 , wherein the conductive contact is a first conductive contact and the integrated circuit further comprises a second conductive contact that contacts the conductive layer from above the first source or drain region.

7 . The integrated circuit of claim 1 , wherein the one or more first semiconductor bodies and the one or more second semiconductor bodies extend in a first direction, and wherein the conductive layer extends in a second direction between the first source or drain region and a dielectric plug, the second direction being orthogonal to the first direction.

8 . The integrated circuit of claim 1 , wherein the conductive layer comprises tungsten.

9 . A printed circuit board comprising the integrated circuit of claim 1 .

10 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a subfin and one or more first semiconductor nanoribbons extending between a first source or drain region and a second source or drain region;
a second semiconductor device having the subfin and one or more second semiconductor nanoribbons extending between the first source or drain region and a third source or drain region;
a dielectric layer adjacent to the subfin of the first semiconductor device and the second semiconductor device;
a conductive layer that extends completely around the first source or drain region between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons; and
a conductive contact extending through a thickness of the dielectric layer and contacting the conductive layer from below the first source or drain region.

11 . The electronic device of claim 10 , wherein the conductive contact further contacts a backside conductive layer below the first source or drain region.

12 . The electronic device of claim 10 , wherein the at least one of the one or more dies further comprises a silicide layer directly between the first source or drain region and the conductive layer.

13 . The electronic device of claim 10 , wherein the conductive contact extends along a sidewall of at least a portion of the subfin below the first source or drain region.

14 . The electronic device of claim 10 , wherein the conductive contact is a first conductive contact and the at least one of the one or more dies further comprises a second conductive contact that contacts the conductive layer from above the first source or drain region.

15 . The electronic device of claim 10 , wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons extend in a first direction, wherein the conductive layer extends in a second direction between the first source or drain region and a dielectric plug, the second direction being orthogonal to the first direction.

16 . An integrated circuit comprising:
a first semiconductor device having one or more first semiconductor bodies extending between a first source or drain region and a second source or drain region; a second semiconductor device having one or more second semiconductor bodies extending between the first source or drain region and a third source or drain region; and a conductive layer that extends completely around the first source or drain region between the one or more first semiconductor bodies and the one or more second semiconductor bodies.

17 . The integrated circuit of claim 16 , further comprising a dielectric layer adjacent to a subfin of the first semiconductor device and the second semiconductor device.

18 . The integrated circuit of claim 17 , further comprising a conductive contact extending through a thickness of the dielectric layer and contacting the conductive layer from below the first source or drain region.

19 . The integrated circuit of claim 16 , wherein the one or more first semiconductor bodies comprises one or more first nanoribbons and the one or more second semiconductor bodies comprises one or more second nanoribbons.

20 . The integrated circuit of claim 16 , further comprising a silicide layer directly between the first source or drain region and the conductive layer.

Assignees

• Intel Corp

Inventors

• Guler Leonard P
• Dewey Gilbert
• Morarka Saurabh
• Abbas Sikandar
• Hasan Mohammad

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title