Diamond field effect transistor and method for producing same

US12457760B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12457760-B2
Application numberUS-202117910325-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2021
Priority dateMar 10, 2020
Publication dateOct 28, 2025
Grant dateOct 28, 2025

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  1. Title

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  5. First independent claim

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Abstract

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Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100 A includes a silicon oxide film 3 A formed on a surface of a non-doped diamond layer 2 A, a non-doped diamond layer 4 A formed on a surface of the non-doped diamond layer 2 A using the silicon oxide film 3 A as a mask, a silicon-terminated layer 5 A formed at an interface between the non-doped diamond layer 2 A and the silicon oxide film 3 A and at an interface between the non-doped diamond layer 4 A and the silicon oxide film 3 A, and a gate electrode 12 A formed on the silicon oxide film 3 A. The FET 100 A operates using the silicon oxide film 3 A and an insulating film 10 A formed on the silicon oxide film 3 A as a gate insulating film 11 A and using the non-doped diamond layer 4 A as each of a source region and a drain region.

First claim

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The invention claimed is: 1. A diamond field effect transistor comprising: a first diamond layer; a gate insulating film including a silicon oxide film provided on a surface of the first diamond layer; a source region and a drain region provided on the surface of the first diamond layer so as to be separated from each other; and a gate electrode provided on the gate insulating film, wherein a silicon-terminated layer containing C—Si bonds formed of bonds between carbon atoms and silicon atoms is provided at an interface between the first diamond layer and the gate insulating film; wherein the source region and the drain region are second diamond layers formed in regions on the surface of the first diamond layer other than a region where the silicon oxide film is formed; and wherein the diamond field effect transistor further comprises: a source electrode and a drain electrode provided on surfaces of the second diamond layers in the source region and the drain region and respectively connected to the source region and the drain region at predetermined intervals from end portions of the source region and the drain region, wherein a hydrogen-terminated layer containing C—H bonds formed of a bond between a carbon atom and a hydrogen atom is provided on the surface of the second diamond layer at least within the predetermined interval. 2. A method for producing a diamond field effect transistor, the method comprising: forming a gate insulating film including a silicon oxide film on a surface of a first diamond layer; forming a source region and a drain region on the surface of the first diamond layer; forming a gate electrode on the gate insulating film; and forming a silicon-terminated layer containing C—Si bonds formed of bonds between carbon atoms and silicon atoms at an interface between the first diamond layer and the silicon oxide film, wherein forming the source region and the drain region on the surface of the first diamond layer includes removing a part of the silicon oxide film to expose a part of the surface of the first diamond layer, and selectively epitaxially growing a second diamond layer on the exposed surface of the first diamond layer, and wherein the method further comprises: forming a silicon-terminated layer including C—Si bonds formed of bonds between carbon atoms and silicon atoms at an interface between the second diamond layer and the silicon oxide film, wherein forming the silicon-terminated layer containing the C—Si bonds at the interface between the first diamond layer and the silicon oxide film, forming the silicon-terminated layer containing the C—Si bonds at the interface between the second diamond layer and the silicon oxide film, and selectively epitaxially growing the second diamond layer on the exposed surface of the first diamond layer, are performed simultaneously by a plasma treatment in the same reducing atmosphere. 3. A method for producing a diamond field effect transistor, the method comprising: forming a gate insulating film including a silicon oxide film on a surface of a first diamond layer; forming a source region and a drain region on the surface of the first diamond layer; forming a gate electrode on the gate insulating film; and forming a silicon-terminated layer containing C—Si bonds formed of bonds between carbon atoms and silicon atoms at an interface between the first diamond layer and the silicon oxide film, wherein forming the source region and the drain region on the surface of the first diamond layer includes removing a part of the silicon oxide film to expose a part of the surface of the first diamond layer, and selectively epitaxially growing a second diamond layer on the exposed surface of the first diamond layer, and wherein the method further comprises: forming a source electrode and a drain electrode on surfaces of the second diamond layers respectively connected thereto at predetermined intervals from end portions of the silicon oxide film, and forming a hydrogen-terminated layer containing C—H bonds formed of bonds between carbon atoms and hydrogen atoms on the surface of the second diamond layer at least within the predetermined interval.

Assignees

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Classifications

  • into semiconducting carbon, e.g. diamond or semiconducting diamond-like carbon · CPC title

  • Carbon, e.g. diamond-like carbon · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • the semiconductor being diamond, semiconducting diamond-like carbon or graphene · CPC title

  • Diamond · CPC title

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What does patent US12457760B2 cover?
Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100 A includes a silicon oxide film 3 A formed on a surface of a non-doped diamond layer 2 A, a non-doped diamond layer 4 A formed on a surface …
Who is the assignee on this patent?
Univ Waseda
What technology area does this patent fall under?
Primary CPC classification H10D30/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).